超大规模集成电路互连系统的布线构造对散热的影响

应用一个三层互连布线结构研究了诸多因素尤其是布线的几何构造对互连系统散热问题的影响,并对多种不同金属与介质相结合的互连布线的散热情况进行了详细模拟.研究表明互连线上焦耳热的主要散热途径为金属层内的金属线和介质层中热阻相对小的路径.因此互连系统的几何布线对系统散热具有重要影响.在相同条件下,铝布线系统的温升约为铜布线的ρAl/ρCu倍.此外,模拟了0.13μm工艺互连结构中连接功能块区域的信号线上的温升情况,探讨了几种用于改善热问题的散热金属条对互连布线的导热和附加电容的影响.     

Influence of Interconnection Configuration on Thermal Dissipation of ULSI Interconnect Systems

应用一个三层互连布线结构研究了诸多因素尤其是布线的几何构造对互连系统散热问题的影响,并对多种不同金属与介质相结合的互连布线的散热情况进行了详细模拟.研究表明互连线上焦耳热的主要散热途径为金属层内的金属线和介质层中热阻相对小的路径.因此互连系统的几何布线对系统散热具有重要影响.在相同条件下,铝布线系统的温升约为铜布线的ρAl/ρCu倍.此外,模拟了0.13μm工艺互连结构中连接功能块区域的信号线上的温升情况,探讨了几种用于改善热问题的散热金属条对互连布线的导热和附加电容的影响.     

铜互连布线及其镶嵌技术在深亚微米IC工艺中的应用

近几年来 ,随着 VLSI器件密度的增加和特征尺寸的减小 ,铜互连布线技术作为减小互连延迟的有效技术 ,受到人们的广泛关注。文中介绍了基本的铜互连布线技术 ,包括单、双镶嵌工艺 ,CMP工艺 ,低介电常数材料和阻挡层材料 ,及铜互连布线的可靠性问题     

一种可重构算子阵列结构的功耗评估方法

介绍了一种面向新型FPGA结构—可重构算子阵列的功耗评估方法。分析了可重构算子阵列结构的功耗构成,同现有的功耗评估方法进行对比,提出基于最大功耗的评估策略。可重构算子和互连单元采用自动测试矢量生成(ATPG)方法计算最大功耗,互连线段的功耗则通过RC等效模型得到。将所有被使用的资源功耗相加,得到该设计所对应的最大功耗值,作为结构探索和在实际应用中阵列规模选取、布局布线优化的指导。     

互连、布线、隔离与装架工艺

0210762铜互连布线及其镶嵌技术在深亚微米IC工艺中的应用〔刊〕/张兆强//固体电子学研究与进展.-2001,21(4).-407～414(D) 近几年来,随着VLSI器件密度的增加和特征尺寸的减小,铜互连布线技术作为减小互连延迟的有效技术,受到人们的广泛关注。文中介绍了基本的铜互连布线技术,包括单、双镶嵌工艺,CMP工艺,低介电常数材料和阻挡层材料,及铜互连布线的可靠性问题。     

基于拓扑分析的多层通道布线算法

本文提出了一种基于拓扑分析的多层通道布线算法。算法把整个布线过程分成拓扑分层和物理布线两个部分。拓扑分层利用线段交叠图及模拟退火算法解决线段分层及通孔最少化问题，物理布线过程引入虚拟走线道解决交叉问题，再利用轮廓线跟踪的方法来决定最终确定各线段的布线位置。算法还解决了多层布线分层的管脚约束问题和相邻约束问题。实验结果表明，这是一种有效的方法。     

MCM-D多层金属布线互连退化模式和机理

介绍了MCM-D多层金属互连结构的工艺及材料特点，并就Cu薄膜布线导体的结构特点和元素扩散特性。说明了多层布线互连退化的模式和机理，以及防止互连退化的技术措施，实验分析表明，Au/Ni/Cu薄膜布线结构的互连退化原因是，Cu元素沿导带缺陷向表层扩散后，被氧化腐蚀，导致互连电阻增大，而Cu元素在温度应力作用下向PI扩散，导致PI绝缘电阻下降。     

半导体封装工艺面临的挑战

集成电路元器件密度与性能的不断提高是以集成电路关键尺寸的不断缩小和芯片内信号互连布线不断复杂化,布线层数不断增加为代价的。     

多端互连线网络布线时延的研究

互连线时延是集成电路设计中非常重要的影响因素。本文根据Elmore延迟模型推导出多端互连线的延迟估算公式，得出了在满足设计规则的前提下，多端互连线网络应尽量遵守的布线规则，即互连线之间不要有重叠，且从源点到每个终点都要走最短的曼哈顿路径。这种布线规则可以在不增加芯片面积的基础上使互连线时延减少，这对指导高速IC芯片的版图设计有重要的理论和实践指导意义。     

Raphael-深亚微米集成互连参数仿真优化系统

针对超深亚微米层次下的金属互连设计,使用Raphael(集成布线互连)仿真系统完成了互连寄生效应参数的提取。介绍了Raphael仿真系统的主要功能及基本应用,并分析了常规集成布线互连参数模型。采用二层跨越式互连结构,对寄生电阻、电容参数进行了仿真,并得到电流密度的分布结果。这些参数的提取及验证对电路的布局设计是十分重要的。     

High electric conduction property of composite copper-clad steelwire

The authors of this paper discover the high electric conduction property of the composite copper-clad steel wire; that is to say, in a specific frequency domain, its electric conduction property is higher than that of copper wire having the same diameter. This paper describes the relationship between this high conduction property as a function of the frequency and structure of the wire and points out that the property results from the reflection of an electromagnetic (EM) wave at the interface inside the composite wire     

铝键合丝弧高、跨度与可靠性的研究

铝丝键合作为一项半导体产品的封装工艺,被广泛用于连接半导体器件内具有铝焊盘4的芯片与其它元件。然而,如果产品内铝丝连接设计或者键合工艺参数超出铝丝材料承受能力,会降低产品的可靠性。本文以铝丝键合失效案例为起始,设计铝丝键合工艺研究试验,对铝丝所能承受的最高弧度和最大跨度进行了讨论和总结,并提出修改意见。通过对比调整前后产品内铝键合丝拉断力和拉断力标准差,证明修改后该产品可靠性明显得到了提升,也论证本文更改建议的正确性。     

基于STM32的短纤尾丝实时检测方法

聚酯纤维生产工艺中,会有定期修板作业,需要将丝束切断,从而产生尾丝。尾丝在原丝中会影响成品质量,为提高产品质量,解决传统生产中由人工判断尾丝所带来的误差,本文实现了一种基于STM32的尾丝检测方法。通过对导丝轮信号的采集,并经过相关算法的处理,能够准确的记录尾丝产生的时间。本装置在仪征化纤有限公司短纤中心投入使用,证实有效。本文详细介绍了尾丝检测原理、系统设计、硬件设计、软件设计等。     

钢丝绳断丝信号的空间域划分及在小波变换下的频域特征提取

频域特征是钢丝绳损伤定量识别的一个重要特征.文中对钢丝绳断丝信号进行了空间域划分和小波变换下的频域特征提取,并用小波网络进行断丝的定量识别.实践结果表明:该方法能够在频域上清楚地区分噪声和损伤信号,提高了钢丝绳断丝检测的能力.     

Comparison of the copper and gold wire bonding processes for LED packaging

Wire bonding is one of the main processes of the LED packaging which provides electrical interconnection between the LED chip and lead frame.The gold wire bonding process has been widely used in LED packaging industry currently.However,due to the high cost of gold wire,copper wire bonding is a good substitute for the gold wire bonding which can lead to significant cost saving.In this paper,the copper and gold wire bonding processes on the high power LED chip are compared and analyzed with finite element simulation.This modeling work may provide guidelines for the parameter optimization of copper wire bonding process on the high power LED packaging.     

Optimizing resistance of round hollow wire at high frequency

The results and methods of calculation of resistance of hollow wire in gigahertz range by Bessel function are given. According to the results of computation, it is found that the resistor of conductor can be optimized using hollow wire with specific wall thickness. At high frequency the current distribution across a circular hollow wire is at surface of wire, which is called skin depth. We found that optimum wall thickness is proportional to skin depth and the phase abrupt change point of H field. Theoretical analysis and mechanism optimized round hollow wire will be presented in this paper. The calculation indicates that cylindrical hollow wire can be optimized to decrease resistance above 8%.     

Improving the deflection of wire bonds in stacked chip scale package (CSP)

The deformation of gold wire bonds during transfer molding of stacked chip scale package (CSP) can seriously cause wire crossover and shorting. The major challenges of the stacked CSP development are to reduce the wire sweep (deflection), and make the sufficient space clearance between the wires of first to second die. In this paper, M shape wire looping program is developed to increase the wire sweep resistance in the stacked CSP. Both linear elastic finite element analysis and experiments based on wire bonding and molding process evaluation are conducted. It is found that M shape looping program is much better than conventional normal wire shape in terms of wire sweep resistance after molding. X-ray and scanning electronic microscopy (SEM) can verify the improvement of wire deflection after chemical de-capsulation. It is believed that using M shape looping program can efficiently overcome the risk of wire shorting and improve the yield of wire bonds in high volume production of stacked CSP.     

A full-wave model of wire structures with arbitrary cross sections

Transmission lines with rectangular cross sections are usually used in integrated circuit (IC) and computer chip problems. In this paper, a full-wave method is proposed based on an efficient wire model to analyze transmission-line circuits, where the cross sections of wires can be arbitrary. Comparing the existing wire models in the method of moments, it has been shown that the best performance occurs when the current is assumed to flow along the electrical axis of a wire and the testing is on the whole surface if two wires are very close. The physical significance of such modeling implies that the surface current on a wire is equivalent to a current filament along the electrical axis. For a single round wire, the electrical axis is exactly the same as its geometrical axis. For two parallel round wires, the electrical axis of each wire is located at the image position of the other wire. In this paper, a general wire model is proposed to determine electrical axes of wires with arbitrary cross sections by solving a static problem. Then, full-wave formulations are derived for wire structures with rectangular cross sections, which are the most important for IC and computer-chip problems. Numerical simulations are given to test the validity and accuracy of the proposed method.     

Comparison of the copper and gold wire bonding processes for LED packaging

Wire bonding is one of the main processes of the LED packaging which provides electrical interconnection between the LED chip and lead frame. The gold wire bonding process has been widely used in LED packaging industry currently. However, due to the high cost of gold wire, copper wire bonding is a good substitute for the gold wire bonding which can lead to significant cost saving. In this paper, the copper and gold wire bonding processes on the high power LED chip are compared and analyzed with finite element simulation. This modeling work may provide guidelines for the parameter optimization of copper wire bonding process on the high power LED packaging.