一种基于亚阈值区特性的CMOS四象限模拟乘法器

讨论了基于ＭＯＳ晶体管亚阈值区特性的ＣＭＯＳ四象限模拟乘法器的设计。分析了四种乘法器核的直流传输特性，给出的ＰＳＰＩＣＥ模拟结果验证了理论分析。模拟结果表明，对于电源电压为１．５Ｖ（或±１．５Ｖ），当输入电压范围限于±０．０８Ｖ时，非线性误差小于１％；－３ｄＢ带宽约为３４０ｋＨｚ，静态功耗小于１μＷ。给出的乘法器核可应用在便携式电子系统模拟信号处理电路中，特别适于在神经网络系统中的应用。     

一种高性能的CMOS四象限模拟乘法器

本文介绍了一种带预处理电路的ＣＭＯＳ四象限模拟乘法器，对其预处理电路（有源衰减器及电平位移电路）和乘法器核心电路的非线性误差作了详细的讨论．设计采用３微米Ｎ阱硅栅ＣＭＯＳ工艺，并给出了电路的ＳＰＩＣＥ模拟结果．当电源电压为±５Ｖ时，功耗小于６．５ｍＷ，线性输入电压范围约为±４Ｖ；当输入电压范围限于±３Ｖ内时，总谐波失真和非线性误差均小于０．３３％，－３ｄＢ带宽为１３．０ＭＨｚ和２．２ＭＨｚ；当输入电压范围限于±２Ｖ内时，总谐波失真小于０．１８％，具有良好的性能．     

一种结构简单的低压CMOS四象限模拟乘法器

提出了一种结构简单、采用有源衰减器的低压ＣＭＯＳ四象限模拟乘法器。详细分析了电路的结构和设计原理,给出了电路的ＰＳＰＩＣＥ模拟结果。模拟结果表明,当电源电压为±１．５Ｖ时,功耗小于８０μＷ,线性输入电压范围约为±０．５Ｖ;当输入电压范围限于±０．３Ｖ时,非线性误差小于１．３％;－３ｄＢ带宽约为３．２ＭＨｚ。该乘法器电路可应用于低压模拟信号处理电路中。     

±5V高频四象限CMOS模拟乘法器

提出了一种新型四象限ＣＭＯＳ模拟乘法器电路,其核心结构为线性化压控源耦对。基于ＭＯＳＩＳ２μｍｐ－阱ＣＭＯＳ工艺参数的ＰＳＰＩＣＥ模拟结果表明：当电源电压为±５Ｖ,输入范围为±４Ｖ时,非线性误差小于０．９％,乘法运算误差小于１．０％;在±３Ｖ的人非线性误差小于０．４％,乘法运算误差小于０．７％;－３ｄＢ带宽一端为１３０ＭＨＺ,另一端为７２０ＭＨＺ;整个电路静态功耗为４．９０ｍＷ。     

短沟道CMOS／SIMOX器件与电路的制造

本文简要介绍短沟道ＣＭＯＳ／ＳＩＭＯＸ器件与电路的研制。在自制的ＳＩＭＯＸ材料上成功地制出了沟道长度为１．０μｍ的高性能全耗尽ＳＩＭＯＸ器件和１９级ＣＭＯＳ环形振荡器。Ｎ管和Ｐ管的泄漏电流均小于１×１０－１２Ａ／μｍ，在电源电压为５Ｖ时环振电路的门延迟时间为２８０ｐｓ。     

一种1.5～2 μm双掺杂多晶硅栅CMOS工艺研究

采用常规Ｐ阱硅栅ＣＭＯＳ改进工艺,进行１．５￣２μｍＣＭＯＳ工艺研究。与常规工艺相比,做出的ＰＭＯＳ管漏源击穿电压可达１８￣２３Ｖ,５Ｖ工作电压下沟道调制效应较小,相应的欧拉电压可达２５￣３０Ｖ,工艺特点在于采用了硼掺杂多晶硅作ＰＭＯＳ管栅电极,磷掺杂多晶硅作ＮＭＯＳ管栅电极。     

微功率精密三电源监控器

Ｌｉｎｅａｒ技术公司的ＬＴＣ１３２６２５是供多电源电压系统用的一款三电源监控器。它可同时监控２５Ｖ、３３Ｖ和可调输入电压，保证±０７５％的阈值精度，２０μＡ电源电流。它以微功率工作、小尺寸（８端脚ＳＯ和ＭＳＯＰ封装）和高精度电源监控。其典型...     

ROHM公司CD／CDROM用集成电路一览表（续）

ＲＯＨＭ公司ＣＤ／ＣＤＲＯＭ用集成电路一览表（续）音频数模转换器品名电源电压（Ｖ）功能２倍转发器数字滤波器去加重衰减器特点封装ＢＵ９４８０Ｆ３．０～５．５电阻串方式○○小型封装，适应２ｆｓＤＩＰ８ＳＯＰ８ＢＵ９４８３ＦＳ５．０电阻串方式○○○用于３...     

8位精度200MHz流水线结构CMOS电压比较器

提出了一种新颖的高速ＣＭＯＳ电压比较器的电路结构，它由一个差分输入组、两组串 ＣＭＯＳ锁存电路和两个ＣＭＯＳ倒相器所组成，并且在外部的三相不交叠时钟信号控制下进行流水线操作。整个电路根据标准的双吕布线１．５μｍ，ｎ阱工艺设计规则和工艺参数进行设计版图面积为为１００μｍ×８０μｍ。整个电路在５Ｖ单电源从电条件下进行具有８位精度的电压比较工作，在以最大采样频率（２００ＭＨｚ）工作时，功耗仅为１．２ｍＷ     

双多晶硅栅SOI MOS器件的研究

采用多晶硅栅全耗尽ＣＭＯＳ／ＳＩＭＯＸ工艺成功研制出多晶硅栅器件,其中Ｎ＋栅ＮＭＯＳ管的阈值电压为０．４５Ｖ,Ｐ＋栅ＰＭＯＳ管的阈值电压为－０．２２Ｖ,在１Ｖ和５Ｖ电源电压下多晶硅栅环振电路的单级门延迟时间分别为１．７ｎｓ和３５０ｐｓ,双多晶硅栅ＳＯＩ技术将是低压集成电路的一种较好选择。     

Design and implementation of current mode circuit for digital modulation

This paper proposes a new current-mode digital modulation circuit. The proposed circuit is MOS only hence, easily integrable. It employs an Extra X Current Conveyor (EX-CCII), two MOS transistors as switches, and a two MOS transistor-based active resistor. The amplitude shift keying/phase shift keying/frequency shift keying (ASK/PSK/FSK) modulator is obtained by proper selection of carriers (I_C1, I_C2). This circuit provides the current output signal at high output impedance, which is favorable for cascading. Also, the circuit is employing only MOS transistors, so it can be monolithically IC implementable. The effects of non-idealities and parasitics of the active element on the circuit performance are also investigated in detail. The functionality of the proposed digital modulator is verified through the Cadence Virtuoso tool using 0.18 μm Generic Process Design Kits parameters with the ±0.9 V supply voltage. The total area of the layout is 968.75 μm². Also, the experimental results are verified by using the IC AD-844 and IC CD4007.     

Programmable CMOS current comparator circuit for analogue VLSI neural networks utilizing identical small-dimension MOS transistors†

A programmable CMOS current comparator circuit is presented which employs seven identical small-dimension MOS transistors, and whose threshold current is adjustable without the need to change any of the MOS transistors. Using transistors with W/L of 2/0.6 um and a 5 V supply voltage, the comparator can be programmed to detect currents over the range from 50 nA to 550 μA. With W/L of 3/0.6 μm and a 3.3 V supply voltage, the programmable range is from 20 nA to 365 μA. Simulations for these configurations indicate that the circuit has propagation delays of 4.125 ns and 4-08 ns, respectively.     

一种BiCMOS基准源及其应用

本文分析了ＭＯＳ晶体管的温度特性及其对器件参数的影响，提出了一种ＢｉＣＭＯＳ基准源，它使器件具有良好的温度特性和抗干扰能力。还对具体应用电路的工作原理作了简单的介绍，分析了电路的温度性能及抗干扰能力，并给出应用结果。     

Transistor characteristics with Ta2O5 gatedielectric

As the gate oxide thickness decreases below 2 nm, the gate leakage current increases dramatically due to direct tunneling current. This large gate leakage current will be an obstacle to reducing gate oxide thickness for the high speed operation of future devices. A MOS transistor with Ta₂O₅ gate dielectric is fabricated and characterized as a possible replacement for MOS transistors with ultra-thin gate silicon dioxide. Mobility, I_d-V_d, I_d-V_g, gate leakage current, and capacitance-voltage (C-V) characteristics of Ta₂O₅ transistors are evaluated and compared with SiO₂ transistors. The gate leakage current is three to five orders smaller for Ta₂O₅ transistors than SiO₂ transistors     

New four-quadrant CMOS analogue multiplier

The letter describes a new four-quadrant CMOS analogue multiplier with a simple circuit configuration. This multiplier is based on the current/voltage characteristics of MOS transistors operating in the triode region. The simulation result shows less than 1% distortion for both input signals of 4Vpp when supply voltages of ± 5V are used.     

采用神经MOS晶体管的低压四象限模拟乘法器的设计

神经 MOS晶体管是最近几年才发明出来的一种高功能度的器件。本文以新开发的神经MOS晶体管的 SPICE宏模型为模拟和验证的工具 ,讨论了采用这种器件实现低压四象限模拟乘法器的系统化设计思想和方法。基于这种设计思想和方法 ,设计了一种大输入范围的低压(± 1 .5V)四象限模拟乘法器电路 ,给出的模拟结果验证了理论分析。     

Nonvolatile static read/write memory cell using CMNOS structure

A new type of nonvolatile static read/write memory cell constructed with three MOS transistors and one MNOS transistor is proposed. The MNOS transistor and one of the MOS transistors involved are complementary combined to offer binary states in the Λ-shapedI-Vcurve for memory operation under normal power supply. Upon power failure, the MNOS transistor acts as a back-up element for nonvolatility. The new cell is characterized by advantageous features such as small cell size, simple peripheral circuit, operation with a unipolar power supply and low standby power consumption.     

A fully integrated analog front-end circuit for 13.56 MHz passive RFID tags in conformance with ISO/IEC 18000-3 protocol

A fully integrated analog front-end circuit for 13.56 MHz passive RFID tags is presented in this paper. The design of the RF analog front-end and digital control is based on ISO/IEC 18000-3 MODE 1 protocol. This paper mainly focuses on RF analog front-end circuits. In order to supply voltage for the whole tag chip, a high efficiency power management circuit with a rather wide input range is proposed by utilizing 15.5 V high voltage MOS transistors. Furthermore, a high sensitivity, low power consumption 10% ASK demodulator with a subthreshold-mode hysteresis comparator is introduced for reader-to-tag communication. The tag chip is fabricated in 0.18-μm 2-poly 5-metal mixed signal CMOS technology with EEPROM process. An on-chip 1 kb EEPROM is used to support tag identification, data writing and reading. The core size of the analog front-end is only 0.94×0.84 mm² with a power consumption of 0.42 mW. Measured results show that the power management circuit is able to maintain a proper working condition with an input antenna voltage range of 5.82–12.3 V; the maximum voltage conversion ratio of the rectifier reaches 65.92% when the tag antenna voltage is 9.42 V. Moreover, the power consumption of the 10% ASK demodulator is only 690.25 nW.     

一种CMOS四象限模拟乘法器的设计

本文提出了一种CMOS四象限模拟乘法器。这种乘法器基于MOS晶体管的电流-电压平方关系,采用线性MOS跨导器、悬浮电压发生器和线性MOS电阻完成乘法运算。这种乘法器具有单端输出电压和较好的温度特性。文章比较详细地介绍了电路特点和工作原理,分析了电路的温度性能,并给出了SPICEⅡ的模拟结果。     

Low-power bandgap references featuring DTMOSTs

This paper describes two CMOS bandgap reference circuits featuring dynamic-threshold MOS transistors. The first bandgap reference circuit aims at application in low-voltage, low-power ICs that tolerate medium accuracy. The circuit runs at supply voltages down to 0.85 V while consuming only 1 μW; the die area is 0.063 mm² in a standard digital 0.35-μm CMOS process. The second bandgap reference circuit aims at high accuracy operation (σ=0.3%) without trimming. It consumes approximately 5 μW from a 1.8-V supply voltage and occupies 0.06 mm² in a standard 0.35-μm CMOS process