时延差驱动的门级耗估算算法

提出一种基于ROBDD图和时延差的组合电路门级平均功耗估算算法，该算法适用于单位延迟模型和一般的延迟模型。算法用时匀质Markov链模型描述信号的变化，电路中各节点的开关活动率用功能翻转与毛刺翻转之和来衡量；根据信号之间的再汇聚特性生成超门，构造局部的ROBDD图（最简有序二叉决策图）来估算功能翻转；根据信号到达单元门各输入端之间的延迟差，构造毛刺产生模型，估算毛刺翻转。该算法通过构造 节点的有约束超门缩小了ROBDD的规模；在考虑信号再汇聚而导致的信号相关性的同时，还比较精确地考虑由于延时误差而产生的毛刺功耗。实验结果显示，与Monte-Carlo统计模拟方法相比，算法的估算精度在10％以内，运行速度要快一个数量级。     

基于ATPG的最大功耗估算改进算法

在大规模集成电路芯片的可靠性分析和性能评估中,功耗估算起着重要的作用,文中提出基于ＡＴＰＧ的最大功耗估算改进算法,通过对电路充放电节点分配信号翻转,使电路工作时的动态功耗最大化;研究了路径搜索空间与功耗估值的关系,减少了路径搜索的开销,加快了估算时间;同时将算法扩展到同步时序电路。     

功能部件的输入翻转敏感功耗模型

功耗评估是进行低功耗研究的基础.在高层评估中体系结构级的功耗评估策略主要有两种:基于活动和基于翻转的评估.文章采用了基于输入翻转敏感的方法为功能部件进行功耗建模,该模型考虑了功耗中的数据依赖性,能得到比较精确的功耗评估结果.     

32 nm CMOS工艺的单粒子多点翻转加固锁存器设计

随着集成电路工艺不断改进,电荷共享效应诱发的单粒子多点翻转已经成为影响芯片可靠性的重要因素.为此提出一种有效容忍单粒子多点翻转的加固锁存器:低功耗多点翻转加固锁存器(low power multiple node upset hardened latch,LPMNUHL).该锁存器基于单点翻转自恢复的双联互锁存储单元(dual interlocked storage cell,DICE),构建三模冗余容错机制,输出端级联“三中取二”表决器,可以有效地容忍单粒子多点翻转,表决输出正确逻辑值,不会出现高阻态,可以有效地屏蔽电路内部节点的软错误.该锁存器能够100%容忍三点翻转,四点翻转的容忍率高达90.30%.通过运用高速传输路径、时钟选通技术和钟控表决器,该锁存器有效地降低了功耗.32 nm工艺下SPICE仿真表明,与加固性能最好的三点翻转加固锁存器综合比较,LPMNUHL的延迟平均降低了40.16%,功耗平均降低了44.96%,功耗延迟积平均降低了65.40%,面积平均降低了34.60%,并且对电压/温度波动不敏感.     

可编程逻辑阵列减少毛刺的低功耗布线算法

随着集成电路工艺的进步和集成度的提高,功耗成为制约FPGA发展的主要问题.为此提出一种减少毛刺的FPGA低功耗布线算法.通过修改代价函数,在布线过程中动态地调节信号的路径,使信号到达查找表输入端的时间基本趋于一致,从而减少毛刺,降低电路的动态功耗.该算法从软件方面来减少毛刺,不需要增加任何硬件电路开销.在运算时间相同的情况下,将文中算法与VPR布线算法进行比较.实验结果表明,该算法平均能消除23.4%的毛刺,降低5.4%的功耗,而关键路径延时平均仅增加1%.     

WSN中利用蚁群路径优化的时隙选择重排算法

针对无线传感器网络(WSN)汇聚传输中的数据传输时间和功耗问题,提出了考虑时间同步和唤醒延迟的汇聚传输时隙选择重排算法。将时分多址接入(TDMA)用作介质访问协议,并允许每个节点在传输时隙期间可以发送或接收数据;设计新的WSN数据收集树模型,将传感器节点生成的数据通过无线链路形成的多跳网络发送到汇聚节点,在数据收集树的每条链路上分析时隙顺序,优化时隙选择,并基于蚁群算法优化路径选择,减少传输能量消耗和均衡簇头能量。实验结果表明,提出的算法可以实现显著的数据传输性能提高和功耗节约。     

高层次综合中基于整数线性规划模型的多目标功耗优化算法

考虑峰值周期功耗和峰值模块功耗的同时优化,并尽可能地降低电路的功耗时延乘积指标.利用参数化功能单元库中各个功能模块的具体物理信息,在多供电电压、多调度周期模式下,建立了整数线性规划模型及其相应的6组约束条件,并将高层次综合中的调度过程和功能单元的绑定过程统一起来进行了模型化.文中算法已经成功地应用到自行开发的高层次综合工具之中,算法中得到的数据结果可以直接用于下一步的布图规划.对测试用例的实验进一步说明:同时优化峰值周期功耗和峰值模块功耗可以取得更好的综合结果,并且改善功耗时延乘积项的值(平均降低了30%),提高电路的可靠性和稳定性.     

时延约束下快速门级双电压分配算法

针对门级电压分配算法速度慢的问题,提出了一种时延约束下基于门分组的双电压分配算法。通过门工作在低、高电压下的延时差与时延裕量的比较,将门分为高电压门组和低电压门组;针对违反时延约束的关键路径上的低电压门（称为关键低电压门）,采用最小割法逐渐升高其电压至电路满足时延约束。通过对ISCAS’85标准电路测试的实验结果表明,与已发表的算法比较,不但功耗有一定改进,且算法速度快。     

多移动汇聚节点的无线传感网中基于服务质量的能耗

针对无线传感网（WSN）中传感节点能耗过高、传输时延过长、数据完整性过差的问题,提出一种基于多移动汇聚节点考虑服务质量（QoS）的路由算法——时延敏感和数据完整性（MSTSDI）算法。首先,通过从基站接收信号的强度判断节点的密度,用K-means聚类算法将传感网划分成自治区域;其次,给每个自治区域分配一个移动汇聚节点,利用支持向量回归（SVR）的方法确定移动汇聚节点的轨迹;最后,引入深度引力域和队列引力域,通过Improved-IDDR算法对时延敏感数据包和数据完整性要求高的数据包进行传输。理论分析和仿真表明,与GLRM算法和LEACH算法相比,Improved-IDDR算法的路由策略的能耗下降幅度分别为21.2%和23.7%;而该算法的时延分别降低了15.23%和17.93%;该算法的所传输数据包的完整性也更好。实验结果表明,MSTSDI在传感网络中能够有效提高系统的性能。     

考虑多输入同时翻转的晶体管级时序分析技术

为了克服现有延时模型所遇到的困难,本文对静态时序分析中通过晶体管级电路模拟来计算门延时的方法进行了研究,该技术的关键是延时测试波形的自动生成。文中分析了多输入同时翻转对最大门延时的影响,提出了一种可以用于测试波形生成的多输入同时翻转模型。基于该模型,提出了互补CMOS电路和传输管电路延时测试波形的生成算法。将模拟计算门延时的方法与晶体管级电路的功能模型提取技术结合在一起,实现了一个晶体管级电路的静态时序分析工具-SpiceTime。实验结果表明,SpiceTime的分析结果均大于HSPICE的模拟结果,而且误差不超过2．7％。Spice-Time的分析时间与电路大小成线性关系,单个门的平均分析时间约为0．3秒。实验结果表明,如果使用单信号翻转模型,最大延时最多可以被低估4．8％。     

ScanBist: a multifrequency scan-based BIST method

The authors present ScanBist, a low-overhead, scan-based built-in self-test method, along with its performance in several designs. A novel clock synchronization scheme allows at-speed testing of circuits. This design allows the testing of circuits operating at more than one frequency while retaining the combinational character of the circuit to be analyzed. We can therefore apply scan patterns that will exercise the circuit under test at the system speed, potentially providing a better coverage of delay faults when compared to other self-test methods. Modifications to an existing transition fault simulator account for cases where inputs originating from scan registers clocked at different frequencies drive a gate. We claim to detect transition faults only if the transition originates from the inputs driven by the highest frequency clock. ScanBist is useful at all levels of system packaging assuming that a standard TAP provides the control and boundary scan isolates the circuit from primary inputs and outputs during BIST mode     

On figures of merit in reversible and quantum logic designs

Five figures of merit including number of gates, quantum cost, number of constant inputs, number of garbage outputs, and delay are used casually in the literature to compare the performance of different reversible or quantum logic circuits. In this paper we propose new definitions and enhancements, and identify similarities between these figures of merit. We evaluate these measures to show their strength and weakness. Instead of the number of gates, we introduce the weighted number of gates, where a weighting factor is assigned to each quantum or reversible gate, based on its type, size and technology. We compare the quantum cost with weighted number of gates of a circuit and show three major differences between these measures. It is proved that it is not possible to define a universal reversible logic gate without adding constant inputs. We prove that there is an optimum value for number of constant inputs to obtain a circuit with minimum quantum cost. Some reversible logic benchmarks have been synthesized using Toffoli and Fredkin gates to obtain their optimum values of number of constant inputs. We show that the garbage outputs can also be used to decrease the quantum cost of the circuit. A new definition of delay in quantum and reversible logic circuits is proposed for music line style representation. We also propose a procedure to calculate the delay of a circuit, based on the quantum cost and the depth of the circuit. The results of this research show that to achieve a fair comparison among designs, figures of merit should be considered more thoroughly.      

Orthogonal Algorithm of Logic Probability and Syndrome-Testable Analysis

A new method,orthogonal algoritm,is presented to compute the logic probabilities(i.e.signal probabilities)accurately,The transfer properties of logic probabilities are studied first,which are useful for the calculation of logic probability of the circuit with random independent inputs.Then the orthogonal algoritm is described to compute the logic probability of Boolean function realized by a combinational circuit.This algorithm can make Boolean function “ORTHOGONAL”so that the logic probabilities can be easily calculated by summing up the logic probabilities of all orthogonal terms of the Booleam function.     

基于转换概率及RO结构的硬件木马检测

针对硬件木马倾向于在电路低转换概率节点插入的问题,提出了一种在这些节点处构建环形振荡器（RO）结构的方法来检测硬件木马。该方法首先计算电路节点的转换概率并挑选出低于转换概率阈值的节点,然后在挑选出的节点处构建RO结构,通过RO延时的变化进行木马的检测。实验以ISCAS’85基准电路为基础,并在Spartan6 FPGA开发板实现。实验结果表明,在可接受的面积和功耗开销下,可以检测到仅有一到两个门的小型木马电路,弥补了旁路信号分析法检测小型木马的不足。     

A Network Security Risk Assessment Method Based on a B_NAG Model

Computer networks face a variety of cyberattacks. Most network attacks are contagious and destructive, and these types of attacks can be harmful to society and computer network security. Security evaluation is an effective method to solve network security problems. For accurate assessment of the vulnerabilities of computer networks, this paper proposes a network security risk assessment method based on a Bayesian network attack graph (B_NAG) model. First, a new resource attack graph (RAG) and the algorithm E-Loop, which is applied to eliminate loops in the B_NAG, are proposed. Second, to distinguish the confusing relationships between nodes of the attack graph in the conversion process, a related algorithm is proposed to generate the B_NAG model. Finally, to analyze the reachability of paths in B_NAG, the measuring indexs such as node attack complexity and node state transition are defined, and an iterative algorithm for obtaining the probability of reaching the target node is presented. On this basis, the posterior probability of related nodes can be calculated. A simulation environment is set up to evaluate the effectiveness of the B_NAG model. The experimental results indicate that the B_NAG model is realistic and effective in evaluating vulnerabilities of computer networks and can accurately highlight the degree of vulnerability in a chaotic relationship.     

基于蚂蚁路径的时序电路故障诊断算法

提出了一种VLSI时序电路自动测试型生成(Automatic test pattern generation，ATPG)的新算法。传统ATPG算法采用局部状态转换图或收集门级电路的知识以及提取电路规则来解决时序电路ATPG的困难。本算法引入新的模型，着重解决了ATPG中的计算冗余问题。在蚂蚁路径模型的基础上，前向搜索得到了重建，故障点的前向传输和回溯归结到了单一路径之上．而该路径上可能分布着许多待测的故障点，从而改善了以往时序电路ATPG算法中搜索重复而导致的计算冗余问题，同时，最小测试向量的获取为数学定理所证明。最后在Benchmark电路上进行的与ILP算法的比较试验表明，本算法具备同样的故障覆盖率，且速度更快。     

IDDT: Fundamentals and Test Generation

It is the time to explore the fundamentals of IDDT testing when extensive work has been done for IDDT testing since it was proposed.This paper precisely defines the concept of average transient current(IDDT) of CMOS digital ICs,and experimentally analyzes the feasibility of IDDT test generation at gate level.Based on the SPICE simulation results,the paper suggests a formula to calculate IDDT by means of counting only logical up-transitions,which enables IDDT test generation at logic level.The Bayesian optimization algorithm is utilized for IDDT test generation.Experimental results show that about 25% stuck-open faults are with IDDT testability larger than 2.5,and likely to be IDDT testable.It is also found that most IDDT testable faults are located near the primary inputs of a circuit under test.IDDT test generation does not require fault sensitization procedure compared with stuck-at fault test generation.Furthermore,some redundant stuck-at faults can be detected by using IDDT testing.     

业务过程的扩展广义随机Petri网模型

为建立能够描述外部环境、业务操作耗时服从一般分布的业务过程性能模型,引入扩展广义随机Petri网.用容纳有无穷多托肯的输入库所描述建模对象外部环境,用闸门变迁控制外部环境对建模对象的输入,为非立即变迁绑定一个任意分布时间延迟随机变量.最后给出一个建模实例.     

串扰时延故障的SAT-ATPG算法研究

随着芯片运行速度不断提高,对串扰时延的测试已成为一个迫切需要解决的问题;文中提出一种面向多条攻击线的受害线上最大串扰噪声的测试生成方法;此方法建立了串扰通路时延故障模型、分析了布尔可满足性问题、讨论了七值逻辑,研究了串扰时延故障测试转换为CNF的逻辑表达式,在非鲁棒测试条件下约简CNF范式,并提出了串扰时延故障的SAT-ATPG算法;最后通过实例分析,对本文算法进行验证;结果表明:该算法对串扰时延故障的测试矢量的生成是有效的。