Scan BIST with biased scan test signals

The conventional test-per-scan built-in self-test （BIST） scheme needs a number of shift cycles followed by one capture cycle. Fault effects received by the scan flipflops are shifted out while shifting in the next test vector like scan testing. Unlike deterministic testing, it is unnecessary to apply a complete test vector to the scan chains. A new scan-based BIST scheme is proposed by properly controlling the test signals of the scan chains. Different biased random values are assigned to the test signals of scan flip-flops in separate scan chains. Capture cycles can be inserted at any clock cycle if necessary. A new testability estimation procedure according to the proposed testing scheme is presented. A greedy procedure is proposed to select a weight for each scan chain. Experimental results show that the proposed method can improve test effectiveness of scan-based BIST greatly, and most circuits can obtain complete fault coverage or very close to complete fault coverage.     

基于SRIO传输的高速时钟电路的优化设计

随着系统电路工作频率的不断越高,在应用中对系统互连和电路间的时钟提出了更高的要求。针对在某信号处理系统的设计中,在测试中偶尔出现SRIO链路异常问题,对高速时钟的参数进行了深入分析,发现了时钟信号受到热噪声的影响引起时钟抖动,会导致SRIO链路断开。提出了增加时钟信号的过渡斜率的优化方案,改善了时钟信号的品质,试验证明系统工作稳定可靠,达到了预期效果。     

Boundary scan with built-in self-test

The authors propose a way to merge boundary scan with the built-in self-test (BIST) of printed circuit boards. Their boundary-scan structure is based on Version 2.0 of the Joint Task Action Group's recommendations for boundary scan and incorporates BIST using a register based on cellular automata (CA) techniques. They examine test patterns generated from this register and the more conventional linear-feedback shift register. The advantages of the CA register, or CAR, are its modularity, which allows modification without major redesign, its higher stuck-at fault coverage, and its higher transition fault coverage     

Reasoning about synchronization in GALS systems

Correct design of interface circuits is crucial for the development of System-on-Chips (SoC) using off-the-shelf IP cores. For correct operation, an interface circuit must meet strict synchronization timing constraints, and also respect sequencing constraints between events dictated by interfacing protocols and rational clock relations. In this paper, we propose a technique for automatically analyzing the interaction between independently specified synchronization constraints and sequencing constraints between events. We show how this analysis can be used to derive delay constraints for correct operation of interface circuits in a GALS system. Our methodology allows an SoC designer to mix and match different interfacing protocols, rational clock relations and synchronization constraints for communication between a pair of modules, and automatically explore their implications on correct interface circuit design.     

考虑时延偏差的数字电路时延测试综述

先进集成电路工艺下,时延测试是数字电路测试的一项重要内容。各种时延偏差来源如小时延缺陷、工艺偏差、 串扰、电源噪声、老化效应等,影响着电路的额定时钟频率,是时延测试中需要考虑的因素。文章在介绍电路时延偏差 问题的各种来源的基础上,给出了针对不同的时延偏差问题所涉及的分析、建模、测试生成与电路设计等关键技术。进 一步介绍了中国科学院计算技术研究所近年来在考虑时延偏差的数字电路时延测试方面所做的研究工作,包括：考虑串 扰/电源噪声的时延测试、基于统计定时分析的测试通路选择、片上时延测量、超速测试、测试优化、在线时序检测等方 面。文章最后对数字电路时延测试技术的发展趋势进行了总结。     

LOCST: A Built-In Self-Test Technique

A built-in self-test technique utilizing on-chip pseudorandom-pattern generation, on-chip signature analysis, a ``boundary scan' feature, and an on-chip monitor test controller has been implemented on three VLSI chips by the IBM Federal Systems Division. This method (designated LSSD on-chip self-test, or LOCST) uses existing level-sensitive scan design strings to serially scan random test patterns to the chip's combinational logic and to collect test results. On-chip pseudorandom-pattern generation and signature analysis compression are provided via existing latches, which are configured into linear-feedback shift registers during the self-test operation. The LOCST technique is controlled through the on-chip monitor, IBM FSD's standard VLSI test interface/controller. Boundary scan latches are provided on all primary inputs and primary outputs to maximize self-test effectiveness and to facilitate chip I/O testing. Stuck-fault simulation using statistical fault analysis was used to evaluate test coverage effectiveness. Total test coverage values of 81.5, 85.3, and 88.6 percent were achieved for the three chips with less than 5000 random-pattern sequences. Outstanding test coverage (≫97%) was achieved for the interior logic of the chips. The advantages of this technique, namely very low hardware overhead cost (≪2%), design-independent implementation, and effective static testing, make LOCST an attractive and powerful technique.     

Built-In Self-Test Structures

A system that includes self-test features must have facilities for generating test patterns and analyzing the resultant circuit response. This article surveys the structures that are used to implement these self-test functions. The various techniques used to convert the system bistables into test scan paths are discussed. The addition of bistables associated with the I/O bonding pads so that the pads can be accessed via a scan path (external or boundary scan path) is described. Most designs use linear-feedback shift registers for both test pattern generation and response analysis. The various linear-feedback shift register designs for pseudorandom or pseudoexhaustive input test pattern generation and for output response signature analysis are presented.     

Single clock partial scan

Existing partial-scan designs use a separate scan clock to simplify scan flip-flop selection and test generation methods. Such designs require multiple clock trees and create clock-signal routing problems that, in general, require tight control of clock skew. The author examines using the system clock for the scan operation and includes experimental results based on ISCAS89 benchmark circuits     

Semiconcurrent Online Testing of Transition Faults through Output Response Comparison of Identical Circuits

We describe a method for online testing of delay faults based on the comparison of output responses of identical circuits. The method allows one of the circuits to participate in useful computations during the testing process, while the other circuit must be idle. We refer to this method as semiconcurrent online testing. While unknown input vectors are applied to the circuit that participates in useful computations, the proposed method applies modified vectors to the idle circuit. In this way, different conditions are created for the detection of delay faults, allowing identical delay faults that affect both circuits to be detected. In designing the modified vectors, we ensure that the expected fault-free responses of the two circuits are identical. We also ensure that the hardware for modifying the vectors applied to the idle circuit will be easy to implement on-chip.     

带时间参数的测试产生

进延测试对于高速集成电路非常重要。本文介绍一个带时间参烽的时延测试产生系统。该系统使用一个时刻逻辑值来表示一个波形,并将输入波形限制为只有唯一的一个输入在０时刻有跳变,其它输入为稳定的０或１,从而实现了波形敏化条件下的时延测试产生,与以往的不考察时间因素的时延测试产生系统相比,带时间参烽的测试产生提高了故障覆盖率,并且更接近于电路的实际。     

Built-In Self-Test Techniques

A system that includes self-test features must have facilities for generating test patterns and analyzing the resultant circuit response. This article surveys the structures that are used to implement these self-test functions. The various techniques used to convert the system bistables into test scan paths are discussed. The addition of bistables associated with the I/O bonding pads so that the pads can be accessed via a scan path (external or boundary scan path) is described. Most designs use linear-feedback shift registers for both test pattern generation and response analysis. The various linear-feedback shift register designs for pseudorandom or pseudoexhaustive input test pattern generation and for output response signature analysis are presented.     

Leakage Current Optimization Techniques During Test Based on Don't Care Bits Assignment

It is a well-known fact that test power consumption may exceed that during functional operation.Leakage power dissipation caused by leakage current in Complementary Metal-Oxide-Semiconductor(CMOS)circuits during test has become a significant part of the total power dissipation.Hence,it is important to reduce leakage power to prolong battery life in portable systems which employ periodic self-test,to increase test reliability and to reduce test cost.This paper analyzes leakage current and presents a kind of leakage current sinmlator based on the transistor stacking effect. Using it,we propose techniques based on don't care bits(denoted by Xs)in test vectors to optimize leakage current in integrated circuit(IC)test by genetic algorithm.The techniques identify a set of don't care inputs in given test vectors and reassign specified logic values to the X inputs by the genetic algorithm to get minimum leakage vector(MLV). Experimental results indicate that the techniques can effectually optimize leakage current of combinational circuits and sequential circuits during test while maintaining high fault coverage.     

Generating tests for delay faults in nonscan circuits

A delay test method that allows any sequential-circuit test generation program to produce path delay tests for nonscan circuits is presented. Using this method, a given path is tested by augmenting the netlist model of the circuit with a logic block, in which testing for a certain single stuck-at fault is equivalent to testing for a path delay fault. The test sequence for the stuck-at fault performs all the necessary delay fault test functions: initialization, path activation, and fault propagation. Results on benchmarks are presented for nonscan and scan/hold modes of testing     

A built-in test module for fault isolation

A broad-level implementation of signature analysis that uses a built-in test module called a testing switch is presented. It is shown how board designers can incorporate the testing-switch modules to reduce the time it takes to isolate faulty chips. Both the test time and the power overhead are better with the testing-switch implementation than with schemes using built-in logic block observer circuits. The proposed technique is especially useful when boundary scan and self-test cannot be implemented in every chip of a board     

基于IEEE1149.4的差分测试方法的研究与应用

IEEE1149．4标准（DOT4）为解决数模混合电路的边界扫描测试提供了有效的方法,对于数模混合差分电路的互联测试,一直是数模混合电路中巨联测试的重点之一,介绍了一种基于此标准的差分互联电路的测试方法以及差分模拟边界扫描单元的应用,对混合差分电路实现了简荤互联和扩展互联的边界扫描测试,从而提高了差分电路互联测试的能力。     

Desing and self-test for switched-current building blocks

This switched-current memory cell with a built-in self-test option serves as a building block for a range of analog functions. As an example application, the authors present a divide-by-two circuit for reference signal generation in algorithmic A/D converters. They also describe two self-test approaches for these building blocks and evaluate their effectiveness. The self-test functions are easy to apply, require very little overhead, and result in fault coverage up to 95% for shorts and 60% for open circuits. Analysis reveals that 100% testability may not be achievable in a cost-effective way for mixed-signal circuits     

基于FPGA的内建自测试的实现研究

内建自测试技术源于激励-响应-比较的测试机理,信号可以通过边界扫描传输到芯片引脚,因而即使BIST本身发生故障也可以通过边界扫描进行检测;为了解决大规模SOC芯片设计中BIST测试时间长和消耗面积大的问题,提出了一种用FPGA实现BIST电路的方法,对测试向量发生器、被测内核和特征分析器进行了研究;通过对被测内核注入故障,然后将正常电路和注入故障后的电路分别进行仿真,比较正常响应和实际响应的特征值,如果相等则认为没有故障,否则发生了特定的故障;利用ModelSim SE 6.1f软件仿真结果表明了该方法的正确有效性和快速性。     

Serial interfacing for embedded-memory testing

A serial interfacing scheme in which several embedded memories share the built-in, self-test circuit is presented. For external testing, this approach requires only two serial pins for access to the data path. There is considerable savings in routing area, and fewer external pins are needed to test random-access memories with wide words, such as those in application-specific integrated circuits for telecommunications. Even though the method uses serial access to the memory, a test pattern is applied every clock cycle because the memory itself shifts the test data. The method has been adapted to four common algorithms. In implementations of built-in self-test circuitry on several product chips, the area overhead was found to be acceptable