三维集成电路中硅通孔缺陷建模及自测试/修复方法研究

硅通孔(Through Silicon Via, TSV)是3维集成电路(3D IC)进行垂直互连的关键技术,而绝缘层短路缺陷和凸点开路缺陷是TSV两种常见的失效形式。该文针对以上两种典型缺陷建立了TSV缺陷模型,研究了侧壁电阻及凸点电阻与TSV尺寸之间的关系,并提出了一种基于TSV缺陷电阻端电压的检测方法。同时,设计了一种可同时检测以上两种缺陷的自测试电路验证所提方法,该自测试电路还可以级联起来完成片内修复功能。通过分析面积开销可得,自测试/修复电路在3D IC中所占比例随CMOS/TSV工艺尺寸减小而减小,随TSV阵列规模增大而减小。     

基于热电耦合激励的TSV三维封装内部缺陷识别方法研究

由于硅通孔互连(Through Silicon Via,TSV)三维封装内部缺陷深藏于器件及封装内部,采用常规方法很难检测.然而TSV三维封装缺陷在热-电激励的情况下可表现出规则性的外在特征,因此可以通过识别这些外在特征达到对TSV三维封装内部缺陷进行检测的目的 .文章利用理论与有限元仿真相结合,对比了正常TSV与典型缺陷TSV的温度分布,发现了可供缺陷识别的显著差异.分析结果表明,在三种典型缺陷中,含缝隙TSV与正常TSV温度分布差异最小;其次为底部空洞TSV,差异最大的为填充缺失TSV.由此可知,通过检测热-电耦合激励下的TSV封装外部温度特征,可实现TSV三维封装互连结构内部缺陷诊断与定位.     

一种基于分压电路的绑定后TSV测试方法

对硅通孔（Through Silicon Via, TSV）进行绑定后测试可以有效地提升三维集成电路的性能和良率。现有的测试方法虽然对于开路和桥接故障的测试能力较高,但是对于泄漏故障的测试效果较差,并且所需的总测试时间较长。对此,提出了一种基于分压电路的TSV绑定后测试方法。该方法设计了一种分压电路,进行泄漏故障测试时可以形成一条无分支的电流路径,有效提高了对泄漏故障的测试能力。此外,该方法测试开路故障和泄漏故障时的电流路径不会相互干扰,可以同时测试相邻TSV的开路故障和泄漏故障。实验结果表明,该方法可以测试10 kΩ以下的弱泄漏故障,并且在工艺偏差下依然能够保持较高的测试能力。相比同类测试方法,该方法所需面积开销更小,所需总测试时间更少。     

一种基于仲裁器的键合前硅通孔测试方法

硅通孔(TSV)故障严重降低了三维集成电路的良率和可靠性。为了在制造流程中尽早精确地排除TSV故障,提出了一种基于仲裁器的键合前TSV测试方法。由于高电平信号通过故障TSV的延迟时间小于无故障TSV,比较被测TSV与无故障TSV的延迟时间,即可判断被测TSV是否存在故障,比较结果由仲裁器给出。依次将被测TSV的延迟时间与不同的延迟时间相比,可对其延迟进行区间定位,实现TSV故障分级。实验结果表明,该方案能够检测出开路电阻大于281 Ω的电阻开路故障、泄漏电阻小于223 MΩ的泄漏故障,有效解决了两种TSV故障共存的检测问题。与现有同类方法相比,该方法提高了测试精度,增加了可检测故障范围,并且可以进行故障分级。     

3D-IC中基于时分复用的TSV蜂窝容错设计

三维芯片(3D-IC)通过硅通孔(TSV)技术来实现电路的垂直互连,延续了摩尔定律,但在制造、绑定等过程中,TSV容易引入各类缺陷。添加冗余TSV是解决该问题的有效方法之一,但TSV面积开销大、制造成本高。提出一种基于时分复用(TDMA)的TSV蜂窝结构容错设计方案,它基于时间对信号TSV进行复用。实验结果表明,与一维链式TDMA结构相比,蜂窝TDMA结构提高了30%的故障覆盖率,并且故障覆盖率随着蜂窝阵列的扩展持续提升。在64TSV阵列中,与一维TDMA结构相比,蜂窝拓扑结构的面积开销降低了10.4%。     

海力士开发出全球最大容量的单芯片封装DRAM内存

全球第二大计算机内存芯片厂商海力士半导体周三称,它已经开发出全球最大容量的单芯片封装DRAM内存芯片。海力士在声明中称,通过使用一种名为TSV(硅通孔技术)的新技术,海力士成功地在一个芯片封装中堆叠了8个2 GB DDR3 DRAM内存芯片。TSV技     

三维集成电路中TSV-TSV的耦合分析与优化

TSV-TSV耦合会对三维集成电路的性能造成影响,主要的负面效应就是引入了耦合噪声。为了能够在初期设计阶段准确的估计TSV间的耦合强度,本文首先提出了存在于TSV间的基于二端口网络的阻抗级耦合通道模型,然后推导出了TSV间的耦合强度公式用来描述TSV-TSV耦合效应。通过与三维全波仿真结果的对比,公式的准确度得到了验证。另外,本文提出了一种减小TSV间耦合强度的设计方法。通过SPICE仿真,所提出设计方法不仅可以应用在简单TSV-TSV的电路结构中,还可以应用在含有多个TSV的复杂电路结构中,从而体现了所提出设计方法的可行性,并且为设计者提供了改善三维集成电路电学性能的可能性。     

应用于三维集成的晶圆级键合技术

随着芯片集成度的不断提高以及CMOS工艺复杂度的增加,集成电路的成本及性能方面的问题越来越突出,基于TSV技术的三维集成已成为研究热点,并很有可能是未来集成电路发展的方向.在三维集成中,键合技术为芯片堆叠提供电学连接和机械支撑,从而实现两层或多层芯片间电路的垂直互连.介绍了几种晶圆级三维集成键合技术的特点及研究现状.     

基于主动激励的硅通孔内部缺陷分类识别

硅通孔(TSV)三维封装因其独特的工艺而备受关注,然而内部缺陷的检测一直是限制其进一步发展的难题。主动红外热成像技术是一种新型无损检测方法,具有无接触、高效率等优点,为实现对TSV内部典型缺陷的识别与分类,提出了一种基于激光加热主动激励的TSV内部缺陷分类识别方法。以激光为辐射热源,充分激发TSV内部缺陷,通过理论与仿真分析,掌握不同内部缺陷在主动激励下的外部温度分布表现规律;建立卷积神经网络模型,通过对外部温度分布结果的训练,实现内部缺陷的分类识别。通过试验证明,该方法对典型TSV内部缺陷具有良好的识别能力,识别准确率可达97.12%。利用主动红外热成像检测方法实现了对TSV内部缺陷的有效检测,为三维封装缺陷检测提供了一种快速有效的方法。     

基于TSV的三维集成螺旋电感等效电路模型

基于硅通孔(TSV)技术,可以实现微米级三维无源电感的片上集成,可应用于微波/射频电路及系统的微型化、一体化三维集成。考虑到三维集成电路及系统中复杂、高密度的电磁环境,在TSV电感的设计和使用中,必须对其电路性能及各项参数指标进行精确评估及建模。采用解析方法对电感进行等效电路构建和寄生参数建模,并通过流片测试对模型进行了验证。结果表明,模型的S参数结果与三维仿真结果吻合良好,证实了等效电路构建的精确性。采用所建立的等效电路模型可以提高TSV电感的设计精度和仿真效率,解决微波电路设计及三维电磁场仿真过程中硬件配置要求高、仿真速度慢等问题。     

Three-Dimensional Packaging Technology for Stacked DRAM With 3-Gb/s Data Transfer

A 3-D packaging technology is developed for stacked dynamic random access memory (DRAM) with through-silicon vias (TSVs). Eight different dry etchers were evaluated for deep Si etching. Highly doped poly-Si TSVs were used for vertical traces inside silicon and interconnection between DRAM chips to realize a DRAM-compatible process. Through optimization of process conditions and layout design, a fast poly-Si filling has been obtained. The entire packaging was carried out at the wafer level by using smart chip connection with feedthrough interposer (FTI) technology. A new bump and wiring structure for the FTI has also been developed for fine-pitch and low-cost bonding. Normal operation during DRAM read/write was confirmed on a 512-Mb DRAM with TSVs, with an I/F chip as a memory controller. Simulation and measurement of the transfer function of the FTI wiring showed a 3-Gb/s/pin data transfer capability.     

考虑温度因素的3D芯片TSV容错结构设计

相比于2D芯片,3D芯片具有更高的功率密度和更低的热导率。针对散热问题,多层3D芯片一般采用具有较高热导率的铜填充硅通孔(TSV)。为提高3D芯片的成品率,在温度条件限制下,对3D芯片进行TSV的容错结构设计非常重要。分析了带有TSV的3D芯片温度模型,提出了3D芯片温度模型的TSV修复方法。根据温度要求设计总的TSV数,将这些TSV分为若干个组,每组由m个信号TSV和n个冗余TSV组成,实现了组内和组间信号的TSV修复。实验结果表明,该TSV容错结构不仅有较高修复效率,而且具有较好散热效果。     

Vertical Integration of Stacked DRAM and High-Speed Logic Device Using SMAFTI Technology

A multistrata dynamic random access memory (DRAM) vertically integrated with a complementary metal oxide semiconductor (CMOS) logic device using through-silicon vias (TSVs) and a unique interposer technology was developed for high-performance, power-efficient, and scalable computing. SMAFTI (SMArt chip connection with FeedThrough Interposer) technology, featuring an ultra-thin organic interposer with high-density feedthrough conductive vias, was used for interconnecting the three-dimensionally stacked DRAM and the CMOS logic device . A DRAM-compatible TSV manufacturing process was realized through the use of a “via-first” process and highly doped poly-Si TSVs for vertical traces inside memory dice. A multilayer ultra-thin die stacking process with micro-bump interconnection using a solid-liquid interdiffusion technique was also developed. The thermal aging reliability of the micro-bump interconnection was evaluated by a unique analysis method and its basic reliability was confirmed. Finally, we fabricated a prototype package including stacked DRAM and a CMOS logic device, and observed the combined operation. High-speed 3 Gbit/s signals were successfully transmitted through the fine interposer between the memory and logic.      

RF-TSV design, modeling and application for 3D multi-core computer systems

The state-of-the-art multi-core computer systems are based on Very Large Scale three Dimensional (3D) Integrated circuits (VLSI). In order to provide high-speed vertical data transmission in such 3D systems, efficient Through-Silicon Via (TSV) technology is critically important. In this paper, various Radio Frequency (RF) TSV designs and models are proposed. Specifically, the Cu-plug TSV with surrounding ground TSVs is used as the baseline structure. For further improvement, the dielectric coaxial and novel air-gap coaxial TSVs are introduced. Using the empirical parameters of these coaxial TSVs, the simulation results are obtained demonstrating that these coaxial RF-TSVs can provide two-order higher of cut-off frequencies than the Cu-plug TSVs. Based on these new RF-TSV technologies, we propose a novel 3D multi-core computer system as well as new architectures for manipulating the interfaces between RF and baseband circuit. Taking into consideration the scaling down of IC manufacture technologies, predictions for the performance of future generations of circuits are made. With simulation results indicating energy per bit and area per bit being reduced by 7% and 11% respectively, we can conclude that the proposed method is a worthwhile guideline for the design of future multi-core computer ICs.     

Through Silicon Via (TSV) defect investigations using lateral emission microscopy

Infra-red photoemission microscopy has been applied for the localization of defects in 3D integrated circuits containing Through Silicon Vias (TSVs). For these investigations, the familiar (planar) emission microscopy configuration was extended to allow imaging and emission microscopy on vertical TSV sidewalls, from versatile 3D viewpoints. Flexible viewing orientation was achieved by introducing an additional reflecting surface into the optical path. Precise alignment of the angle of incidence at the air–silicon interface, with sufficient accuracy to ensure no problematic refraction-related errors, was possible using this experimental set-up. Three examples are presented, showing defect localizations and underlying physical leakage mechanisms in TSV structures.     

Novel through-silicon vias for enhanced signal integrity in 3D integrated systems

In this paper, a new type of through-silicon via (TSV) for via-first process namely bare TSV, is proposed and analyzed with the aim of mitigating noise coupling problems in 3D integrated systems for advanced technology nodes. The bare TSVs have no insulation layers, and are divided into two types: bare signal TSVs and bare ground TSVs. First, by solving Poisson''s equation for cylindrical P-N junctions, the bare signal TSVs are shown to be equivalent to conventional signal TSVs according to the simulation results. Then the bare ground TSV is proved to have improved noise-absorption capability when compared with a conventional ground TSV. Also, the proposed bare TSVs offer more advantages to circuits than other noise isolation methods, because the original circuit design, routing and placement can be retained after the application of the bare TSVs.     

Metallization defect detection in 3D integrated components using scanning acoustic microscopy and acoustic simulations

In the context of More than Moore 3D integration concepts, the μm to nm sized failure detection and analysis represents a highly demanding task. In this work, micron sized artificially induced metallization defects in open TSVs are detected by scanning acoustic microscopy (SAM). Micro X-ray computed tomography (μXCT) and scanning electron microscopy (SEM) are used to validate the SAM results. Notably, the SAM results show that the failures for certain TSVs are located at a different position as illustrated by μXCT and SEM. In order to interpret these controversial results, 2D elastodynamic finite integration technique (EFIT) simulations are performed. We discuss the results by taking the excitation of surface acoustic waves (SAWs) or Rayleigh waves into account which are leading to characteristic interference patterns within the TSV. The simulation and understanding of such interference effects can be highly beneficial for the use of SAM with respect to modern failure detection and analyses.     

X-ray inspection of TSV defects with self-organizing map network and Otsu algorithm

Through-silicon via (TSV) is one of the most critical elements in 3D integration, where defects such as unfilled bottom and holes are very common. Thus, defect detection is of great importance to improve products quality. In this work, a non-destructive TSV defect detection method using X-ray imaging is introduced. Seven features representative of TSVs are extracted from the images, and then inputted into a self-organizing map (SOM) network for classification and testing. The results demonstrate that the normal TSVs and defective TSVs can be distinguished obviously by SOM network. The voids inside the TSVs are further located qualitatively using the Otsu algorithm and verified by the SEM images. These prove the feasibility of X-ray inspection of TSV defects with SOM network and Otsu algorithm.     

High aspect ratio copper through-silicon-vias for 3D integration

Three-dimensional (3D) integration, which uses through-silicon-vias (TSVs) to interconnect multiple layers of active circuits, offers significant improvements over planar integrated circuits (ICs) on performance, functionality, and integration density. To address a key issue in 3D integration, the fabrication of high aspect ratio TSVs, this paper presents the bottom-up copper electroplating technique to fill high aspect ratio vias with copper. Deep through-silicon holes with aspect ratio as high as 10:1 are etched using deep reactive ion etching (DRIE) method, and are completely filled with copper using bottom-up copper electroplating technique without forming any voids or seams. Based on this technique, a multi-layer 3D integration method is proposed. This method uses temporary transfer wafer to provide mechanical support to the device wafer during wafer thinning process and to provide the seed layer for copper electroplating. Then bottom-up electroplating is performed to fill the high aspect ratio vias with copper. Experimental results verify the feasibility of the proposed method.