栅槽刻蚀工艺对增强型GaN HEMT器件性能的影响

基于凹槽栅增强型氮化镓高电子迁移率晶体管(GaN HEMT)研究了不同的栅槽刻蚀工艺对GaN器件性能的影响。在栅槽刻蚀方面,采用了一种感应耦合等离子体(ICP)干法刻蚀技术与高温热氧化湿法刻蚀技术相结合的两步法刻蚀技术,将AlGaN势垒层全部刻蚀掉,制备出了阈值电压超过3 V的增强型Al_2O_3/AlGaN/GaN MIS-HEMT器件。相比于传统的ICP干法刻蚀技术,两步法是一种低损伤的自停止刻蚀技术,易于控制且具有高度可重复性,能够获得更高质量的刻蚀界面,所制备的器件增强型GaN MIS-HEMT器件具有阈值电压回滞小、电流开关比(I_ON/I_OFF)高、栅极泄漏电流小、击穿电压高等特性。     

Reduction of Dislocation Density in HVPE-Grown GaN Epilayers by Using In Situ-Etched Porous Templates

In this paper, a method was demonstrated to reduce the dislocation density of GaN film grown by hydride vapor phase epitaxy (HVPE) on an in situ selective hydrogen-etched GaN/sapphire template. The dislocations regions were etched by hydrogen to form cavities. The porous structure was formed on the GaN template grown by metal organic chemical vapor deposition after in situ hydrogen etching. The etching condition was optimized by modulating the etching temperature, pressure, and etching time. Two-step buffer layer growth and high temperature GaN film deposition were carried on the porous template. The growth parameters were optimized to keep the porous structure unfilled. The dislocations originally located in etched cavities could not propagate to the next layer grown by HVPE. Therefore, the dislocation density could be significantly reduced. High crystal quality of GaN is obtained with a low dislocation density. The full width at half-maximum FWHM of (002) is 35 arcs, and the FWHM of (102) is 48 arcs.     

"自上而下"法制备高性能GaN纳米线阵列

针对自下而上生长GaN纳米线的尺寸、形态、取向不易控制的问题,文中采用自上而下刻蚀的方法来制备GaN纳米线材料。以图形化的金属Ni作为掩膜对GaN进行ICP刻蚀,系统研究了刻蚀参数,主要是ICP功率以及RF功率对GaN纳米线形貌以及拉曼、PL光谱的影响,同时也对比了干法刻蚀后,有无湿法处理的影响。研究发现,当ICP功率为1 000 W,RF功率为100 W时,GaN纳米线的拉曼和PL光谱强度较大,表明此功率下刻蚀的纳米线损伤较小。经过KOH浸泡30 min后,GaN纳米线的形貌得到了改善,拉曼和PL光谱强度均优于单纯的干法刻蚀,为下一步器件的制备提供了良好的材料基础。     

等离子体刻蚀凹栅槽影响AlGaN/GaN HEMT栅电流的机理

对等离子体干法刻蚀形成的凹栅槽结构AlGaN/GaN HEMTs肖特基电流增加的机理进行了研究.实验表明,凹栅槽结构AIGaN/GaN HEMTs肖特基栅电流增加一个数量级以上,击穿电压有一定程度的下降.利用AFM和XPS的方法分析AlGaN表面,等离子体干法刻蚀增加了AlGaN表面粗糙度,甚至出现部分尖峰状突起,增大了栅金属与AlGaN的接触面积;另一方面,等离子体轰击使AlGaN表面出现一定量的N空位,相当于栅金属与AlGaN接触界面处出现n型掺杂层,使肖特基结的隧道效应加强,降低了肖特基势垒.由此表明,AlGaN表面粗糙度的增加以及一定量的N空位出现是引起栅电流急剧增大的根本原因.     

Polarization-Engineered Ga-Face GaN-Based Heterostructures for Normally-Off Heterostructure Field-Effect Transistors

Polarization-engineered Ga-face GaN-based heterostructures with a GaN cap layer and an AlGaN/p-GaN back barrier have been designed for normally-off field-effect transistors (FETs). The simulation results show that an unintentionally doped GaN cap and p-GaN layer in the buffer primarily deplete electrons in the channel and the Al_0.2Ga_0.8N back barrier helps to pinch off the channel. Experimentally, we have demonstrated a normally-off GaN-based field-effect transistor on the designed GaN cap/Al_0.3Ga_0.7N/GaN channel/Al_0.2Ga_0.8N/p-GaN/GaN heterostructure. A positive threshold voltage of 0.2 V and maximum transconductance of 2.6 mS/mm were achieved for 80-μm-long gate devices. The device fabrication process does not require a dry etching process for gate recessing, while highly selective etching of the GaN cap against a very thin Al_0.3GaN_0.7N top barrier has to be performed to create a two-dimensional electron gas for both the ohmic and access regions. A self-aligned, selective etch of the GaN cap in the access region is introduced, using the gate metal as an etch mask. The absence of gate recess etching is promising for uniform and repeatable threshold voltage control in normally-off AlGaN/GaN heterostructure FETs for power switching applications.     

Fast patterning and dry-etch of SiNχ for high resolution nanoimprint templates

We developed a simplified nanofabrication process for imprint templates by fast speed electron beam lithography (EBL) and a dry etch technique on a SiNx substrate, intended for large area manufacturing. To this end,the highly sensitive chemically amplified resist (CAR), NEB-22, with negative tone was used. The EBL process first defines the template pattern in NEB-22, which is then directly used as an etching mask in the subsequent reactive ion etching (RIE) on the SiNx to form the desired templates. The properties of both e-beam lithography and dry etch of NEB-22 were carefully studied, indicating significant advantages of this process with some drawbacks compared to when Cr was used as an etching mask. Nevertheless, our results open up a good opportunity to fabricate high resolution imprint templates with the prospect of wafer scale manufacturing.     

高分辨率SiNx纳米压印模板的快速制备工艺

纳米压印技术是近年来国际新兴的纳米光刻技术,具有高分辨率、高效率和低成本等优点。本文结合电子束光刻技术和干法刻蚀技术开发了简洁的纳米压印SiNx光栅模板制造工艺。为提高工艺效率,引进高灵敏度的化学放大胶NEB-22胶（负性胶）作为电子光刻胶,用电子束光刻技术在NEB-22上刻出光栅图形,再利用其作为掩膜,经反应离子刻蚀后,将光栅图形转移到氮化硅上,得到所需模板。文中详细研究了NEB-22胶的电子束光刻特性及其干法刻蚀特性,指出了它作为电子束光刻胶的优点及它相对于铬掩膜而言作为干法刻蚀掩膜的不足。     

掺杂GaN的湿法刻蚀研究

对掺杂GaN的湿法刻蚀研究进行了总结,回顾了不同的湿法刻蚀技术,包括传统的酸碱化学刻蚀和电化学刻蚀。从掺杂GaN的生长过程、表面化学组分和光电性质出发,深入地分析了湿法刻蚀的特性,对比了不同刻蚀方法的原理和效果。考虑到p-GaN的表面氧化层比较厚,接触电阻较大,能带向下弯曲不能进行光增强湿法刻蚀,重点阐述了p-GaN的传统湿法刻蚀和n-GaN的紫外光增强湿法刻蚀技术。与传统化学刻蚀相比,光增强湿法刻蚀具有更为广阔的前景。结合GaN基半导体器件的制作,对湿法刻蚀的主要应用进行了较为详细的归纳。目前,湿法刻蚀和干法刻蚀可以有效结合。将来湿法刻蚀有希望代替干法刻蚀。     

Low damage, Cl/sub 2/-based gate recess etching for 0.3-/spl mu/m gate-length AlGaN/GaN HEMT fabrication

The traditional dry etching for GaN using the Ar/Cl/sub 2/ mixture gas in the reactive ion etching system has been developed. In order to reduce the surface damage, the additional CH/sub 4/ gas is introduced. However, this approach still has the problems of the residual surface damage and low etching selectivity between the AlGaN and GaN materials. Therefore, the following rapid thermal annealing (RTA) at 700/spl deg/C is necessary to recover the surface properties. In this study, we proposed the Ar/Cl/sub 2//CH/sub 4//O/sub 2/ for the GaN gate-recess etching in AlGaN/GaN HEMTs fabrication, which achieves a low surface damage and a high etching selectivity simultaneously. The 0.3 /spl mu/m gate-length AlGaN/GaN HEMTs present a transconductance of 230 mS/mm, an f/sub T/ of 48 GHz, and f/sub max/ of 60 GHz, respectively.     

Dislocation Reduction in GaN on Sapphire by Epitaxial Lateral Overgrowth

采用侧向外延(ELOG)方法,在制作了条形掩膜图形的GaN衬底上用MOCVD生长高质量GaN.AFM,化学湿法腐蚀及TEM分析表明:采用两步法ELOG生长的GaN中,掩膜下方的缺陷被掩膜所阻挡,窗口区内二次生长的GaN的位错也大幅降低;在相邻生长前沿所形成的合并界面处形成晶界;化学湿法腐蚀无法得到关于合并界面处缺陷的信息.侧翼区域中极低的穿透位错使得ELOG GaN适用于在其上制作高性能的氮化物基激光器.     

蓝宝石衬底上侧向外延GaN中的位错降低

采用侧向外延(ELOG)方法,在制作了条形掩膜图形的GaN衬底上用MOCVD生长高质量GaN.AFM,化学湿法腐蚀及TEM分析表明:采用两步法ELOG生长的GaN中,掩膜下方的缺陷被掩膜所阻挡,窗口区内二次生长的GaN的位错也大幅降低;在相邻生长前沿所形成的合并界面处形成晶界;化学湿法腐蚀无法得到关于合并界面处缺陷的信息.侧翼区域中极低的穿透位错使得ELOG GaN适用于在其上制作高性能的氮化物基激光器.     

Polarity control of GaN epilayers grown on ZnO templates

We report the successful growth of Ga-polar GaN epilayers on O-polar ZnO templates pre-deposited on c-sapphire. Prior to GaN growth, NH₃ is exposed onto the ZnO template. The polarity of the GaN layers is confirmed by etching of the surface and by conversion beam electron diffraction (CBED), while the O-polar ZnO is confirmed by CBED. It is suggested that the NH₃ pre-exposure helps form a Zn₃N₂ layer, which possesses inversion symmetry and inverts the crystal from anion polar to cation polar.     

凹栅槽AlGaN/GaN HEMTs器件退火处理效应

研究了如何减小等离子体干法刻蚀导致的大肖特基漏电.用X射线光电能谱(XPS)分析刻蚀前后的AlGaN表面,发现刻蚀后AlGaN表面出现了N窄位,导致肖特基栅电流偏离热电子散射模型,N空位做为一种缺陷使得肖特基结的隧穿几率增大,反向漏电增大,肖特基势垒降低.介绍了一种AlGaN/GaN HEMTs器件退火处理方法,优化退火条件为400℃,Nz氛围退火10min.退火后,栅金属中的Ni与Ga原子反应从而减少N空穴造成的缺陷,器件肖特基反向漏电减小三个量级,正向开启电压升高,理想因子从3.07降低到了2.08.     

Cl2/BCl3感应耦合等离子体GaN刻蚀侧壁形貌研究

基于感应耦合等离子体干法刻蚀技术,对采用Cl2/BCl3气体组分下GaN刻蚀后的侧壁形貌进行了研究。扫描电镜(SEM)结果表明,一定刻蚀条件下,刻蚀后GaN侧壁会形成转角与条纹状褶皱形貌。进一步实验,观察到了GaN侧壁转角形貌的形成过程;低偏压功率实验表明,高能离子轰击是GaN侧壁转角与条纹状褶皱形貌形成的原因。刻蚀过程中,掩蔽层光刻胶经过高能离子一段时间轰击后,其边缘首先出现条纹状褶皱形貌,并转移到GaN侧壁上,接着转角形貌亦随之出现并转移到GaN侧壁上。这与已公开发表文献认为的GaN侧壁条纹状褶皱仅由于掩蔽层边缘粗糙所引起而非刻蚀过程中形成的解释不同。     

低损伤ICP刻蚀技术提高GaN LED出光效率

首先分析了在制作GaN基LED时,采用干法刻蚀技术会对材料的表面和量子阱有源区造成损伤,影响了GaN基LED的内量子效率。针对这个问题,研究实验采用感应耦合等离子反应刻蚀(ICP-RIE)技术,分别选择了氯气/三氯化硼(Cl2/BCl3)气体体系和氯气/氩气(Cl2/Ar)气体体系,通过优化射频功率、ICP功率、气体流量以及相应的真空度,得到了良好的刻蚀端面,对于材料造成的损伤较低,得到更好的I-V特性。实验结果表明,采用低损伤的偏压功率刻蚀后制作的LED器件,出光功率提升一倍以上,同时采用Cl2/Ar气体体系,改善了器件的I-V特性,有效提高了LED的出光效率。     

GaN/SiO_2刻蚀选择比的研究

在干法刻蚀GaN时使用SiO2作为掩蔽物,为了在较快的GaN刻蚀速率下获得良好的GaN/SiO2刻蚀选择比,使用电感耦合等离子刻蚀机(ICP),运用Cl2和Ar作为刻蚀气体,改变ICP功率、直流自偏压、气体总流量、气体组分等工艺条件,并讨论了这些因素对GaN/SiO2刻蚀选择比以及对GaN刻蚀速率的影响。实验结果获得了GaN在刻蚀速率为165nm/min时的GaN/SiO2选择比为8∶1。设备验收时GaN刻蚀速率为70nm/min,GaN/SiO2选择比为3.5∶1,可以应用于实际生产。     

GaN-Based Light-Emitting Diode Prepared on Nano-Inverted Pyramid GaN Template

Using self-aligned $hbox{SiO}_{2}$ nano-spheres as an etching mask, the authors demonstrated the formation of a GaN-based nano-inverted pyramid (NIP) structure. It was found that crystal quality of the GaN epilayer prepared on an NIP/GaN template was significantly better than that prepared with conventional low-temperature GaN nucleation layer. With the NIP structure, it was found that 20-mA light-emitting-diode (LED) output power can be enhanced by 32%, as compared with the conventional LED.      

Digital etching of III-N materials using a two-step Ar/KOH technique

A two-step digital etch technique, based on an argon plasma exposure followed by a 0.2 M boiling KOH surface treatment, is shown to be effective for etching III-N materials. Etching takes place as a result of the fact that damaged nitride material, whose depth can be controlled by the argon reactive ion etching (RIE) plasma, is susceptible to removal in heated solutions of KOH, which has been demonstrated for GaN, AlGaN, and InGaN. The process is shown to be highly linear across a number of digital etch cycles and capable of producing smooth surface morphologies.     

High-Quality Etching of GaN Materials with Extremely Slow Rate and Low Damage

Semiconductors - High-quality gallium nitride etching is highly desirable in electronic device fabrications. For the GaN base devices, the electronic properties largely depended on the etching...     

Wet Etching of (0001) GaN/Al2O3 grown by MOVPE

H₃PO₄, NaOH, and KOH solutions are found to be useful for removing nitrogen depleted layers or damage induced by high temperature annealing or dry etching of metalorganic chemical vapor deposition-grown (0001)GaN/Al₂O₃. Solutions are selective to the (0001)plane of GaN. However, certain flat planes etched without etch pits are exposed by wet etching.