一种新颖的4bit和5bit超宽带GaAs单片数字衰减器

介绍了一种新颖的DC～20GHz的4bit和5bit GaAs单片数字衰减器的设计、制造和测试结果.该衰减器的设计采用纵向思维的方法.最终得到的4bit数字衰减器的主要性能指标是:在DC～20GHz频带内,插入损耗≤3.5dB,最大衰减量15dB,衰减步进1dB,衰减平坦度≤0.2dB,衰减精度≤±0.3dB,两端口所有态的电压驻波比≤1.6,相对于参考态,衰减态的插入相移在-10°～5°以内,芯片尺寸1.8mm×1.6mm×0.1mm.5bit数字衰减器的主要性能指标是:在DC～20GHz频带内,插入损耗≤3.8dB,最大衰减量15.5dB,衰减步进0.5dB,衰减平坦度≤0.3dB,衰减精度≤±0.4dB,两端口所有衰减态的电压驻波比≤1.8,相对于参考态,衰减态的插入相移在-14°～2°以内,芯片尺寸2.0mm×1.6mm×0.1mm.     

0.5μm GaAs PHEMT数字衰减器设计

采用0.5μm GRAs PHEMT工艺设计了两款工作于1～4 GHz的数字衰减器.一款为选择式衰减器,衰减量0.5 dB和15dB,插入损耗≤1 dB,所有衰减状态的输入输出驻波比≤1.7;另外一款为3 bit数字衰减器.衰减步进0.8 dB.最大衰减量5.6 dB,插入损耗≤1 dB,所有衰减状态的输入输出驻波比≤1.8,相对于参考态,衰减态的插入相移在-3°～2°之间.     

24~30 GHz高精度低附加相移数控衰减器

基于0.18 μm CMOS工艺,设计并实现了一种5位高精度低附加相移数控衰减器。该衰减器的衰减动态范围为15.5 dB,步进为0.5 dB。采用了T型衰减结构和SPDT型衰减结构的衰减网络。采用了悬浮栅和悬浮衬底,提高了衰减精度,减小了插入损耗。采用了相位补偿网络,有效降低了衰减器的附加相移。测试结果表明,在24~30 GHz频带范围内,衰减步进为0.5 dB,插入损耗小于8 dB,衰减误差均方根(RMS)小于0.45 dB,附加相移小于±5°。芯片尺寸为1.2 mm×0.3 mm。     

带数字驱动的Ku波段6bit数控衰减器设计北大核心CSCD

采用GaAs增强/耗尽型（E/D）赝配高电子迁移率晶体管（PHEMT）工艺研制了一款带数字驱动的Ku波段6bit数控衰减器微波单片集成电路（MMIC）。该MMIC将数字驱动和6bit数控衰减器集成在一起,数字驱动电路采用的是直接耦合场效应晶体管逻辑（DCFL）电路,6bit数控衰减器由6个衰减基本态级联组成。版图经过合理优化后,最终的MMIC芯片尺寸为2.4mm×1.3mm。测试结果表明,在12~18GHz,芯片可以实现最大衰减量为31.5dB,步进为0.5dB的衰减量控制。衰减64态均方根误差小于0.6dB,附加相移-2°~2.5°,插入损耗小于6.1dB,输入输出驻波比均小于1.5∶1。     

一种7~13 GHz低插损6位数字衰减器

设计了一种基于0.25 μm GaAs p-HEMT工艺的低插损6位数字衰减器。采用Pi型衰减结构与T型衰减结构级联的方式,实现低插入损耗和高衰减精度。采用相移补偿电路减小附加相移,采用幅度补偿电路提高衰减精度。仿真结果表明,在7~13 GHz范围内,该数字衰减器的RMS幅度误差小于0.5 dB,插入损耗小于5.6 dB,10 GHz时1 dB压缩点的输入功率约为29 dBm,附加相移为-7°~+6.5°,输入输出回波损耗小于-11 dB。芯片尺寸为2.50 mm×0.63 mm。     

高性能2 ~ 18GHz 超宽带MMIC 6 位数字衰减器

介绍了一种高性能2～18GHz MMIC 6位GaAs PHEMT数字衰减器的设计、制造和测试结果。研制的单片数字衰减器衰减步进为0.5dB;最大衰减范围为31.5dB;参考态插入损耗<5.71dB;所有衰减态的输入、输出电压驻波比<1.8;衰减精度:+2.31dB/-0.51dB;插入相移:+6.28°/-1.53°;64态幅度均方根误差<1.0dB;64态相移均方根误差<1.3°;芯片尺寸:2.89mm×1.22mm×0.1mm。工艺成品率高达85%。     

一种新颖的DC～50GHz低插入相移MMIC可变衰减器

介绍了一种新颖的 DC～ 5 0 GHz低相移、多功能的 Ga As MMIC可变衰减器的设计与制作 ,获得了优异的电性能。微波探针在片测试结果为 :在 DC～ 5 0 GHz频带内 ,最小衰减≤ 3 .8d B,最大衰减≥ 3 5± 5 d B,最小衰减时输入 /输出驻波≤ 1 .5 ,最大衰减时输入 /输出驻波≤ 2 .2 ,衰减相移比≤ 1 .2°/d B。芯片尺寸 2 .3 3 mm× 0 .68mm× 0 .1 mm。芯片成品率高达 80 %以上 ,工作环境温度达 1 2 5°C,可靠性高 ,稳定性好     

一种新颖的DC—50GHz低插入相移MMIC可变衰减器

介绍了一种新颖的DC－50GHz低相移、多功能的GaAs MMIC可变衰减器的设计与制作，获得了优异的电性能。微波探针在片测试结果为：在DC－50GHz频带内，最小衰减≤3.8dB，最大衰减≥35&;#177;5dB，最小衰减时输入／输出驻波≤1.5，最大衰减时输入／输出驻波≤2.2，衰减相移比≤1.2&;#176;/dB。芯片尺寸为2.33mm&;#215;0.68mm&;#215;0.1mm。芯片成品率高达80％以上，工作环境温度达125℃，可靠性高，稳定性好。     

高性能超宽带单片数字衰减器设计与实现

介绍了一种高性能50MHz～20GHz的超宽带5 bit GaAs数字衰减器的设计、制造和测试结果,并着重介绍实现超宽带的设计.该衰减器通过标准0.5μm离子注入工艺实现.最终的单片衰减器性能如下:插入损耗＜5dB;最大衰减量＞31dB;两端口所有态的电压驻波比＜1.5;所有态衰减精度＜±0.3dB;相位变化量(相对于基态)在-5°～20°之间;1dB压缩点输入功率22dBm(10GHz).     

高性能超宽带单片数字衰减器设计与实现

介绍了一种高性能50MHz～20GHz的超宽带5 bit GaAs数字衰减器的设计、制造和测试结果,并着重介绍实现超宽带的设计.该衰减器通过标准0.5μm离子注入工艺实现.最终的单片衰减器性能如下:插入损耗＜5dB;最大衰减量＞31dB;两端口所有态的电压驻波比＜1.5;所有态衰减精度＜±0.3dB;相位变化量(相对于基态)在-5°～20°之间;1dB压缩点输入功率22dBm(10GHz).     

A bit is a bit is a bit?

Bits are among the most anonymous, most elusive entities in the universe. Bits weigh nothing, occupy no space, obey no physical law, can be created spontaneously from nothingness, and can be endlessly replicated. Each in itself is the merest quantum of the Information Age, yet taken together all those little 1s and 0s are acting as if they were the most important force on the planet. And if you want indestructibility, then a bit is forever. The author briefly discusses the role of the bit in today's society     

利用16位DAC实现20位分辨率的设计

本文提出了一种利用可编程增益放大器提高系统精度的方法，即在精密DAC后端使用两个可鳊程增益放大器(PGA)PGA205从而提高该系统的精度。文章给出了基于TMS320VC5402和AD7846产生任意高精度波形的解决方案。     

一种可变位速率的位同步器的设计与仿真

大部分传统的位同步器是针对固定位速率遥测系统来设计的,这不能满足一些可变位速率遥测接收机的需求。因此,提出一种基于FPGA实现的位同步器的设计,它能适应不同位速率的遥测系统。同时,对这种位同步器的实现进行了仿真,验证其正确性和可实现性。     

Optimal bit rate conversion of MPEG-2 video bit streams

An optimal bit rate conversion scheme for MPEG-2 video bit streams, based on a drift free video transcoder, is proposed. It is shown that optimally transcoded bit streams produce better picture quality than both a cascade of decoder-encoder and than a standard encoder using the original pictures, at the same reduced bit rates     

A 16 bit/spl times/16 bit pipelined multiplier macrocell

A 16 bit/spl times/16 bit pipelined multiplier implemented in a two-layer metal 1.5 /spl mu/m CMOS/BULK technology has been developed. The design is based on the well-known modified Booth algorithm and is capable of operating at a 25 MHz clock rate. The multiplier is designed to be used as a macrofunction within larger chip designs. A structured design approach has been utilized so that reconfiguration of the basic array can be performed. The multiplier macrocell measures 1.7 mm/spl times/1.7 mm.     

Successive bit loading scheme

A new bit loading procedure with a successive loading structure is presented. The optimisation criterion of this scheme is to minimise the bit error rate (BER). This bit loading scheme is applied to an orthogonal frequency division multiplexing (OFDM) transmission system. Based on the measured signal-to-noise ratio (SNRn) values per subcarrier a successive loading structure is developed where the next bit is always loaded onto that subcarrier i which has the lowest BER and maximum remaining SNRi value.     

Television by the bit

The various types of advanced television (ATV) are defined, and the most advanced type, high-definition TV (HDTV), is discussed. The present status of HDTV development in the US, Japan, and Europe is examined. Signal processing requirements for HDTV are briefly considered, and the benefits of and prospects for all-digital HDTV are explored. Video compression techniques, implementation issues, and the future of HDTV are also discussed     

用于14位210 MS/s电荷域ADC的4.5位子级电路

该文提出了一种用于高速高精度电荷域流水线模数转换器(ADC)的电荷域4.5位前端子级电路。该4.5位子级电路使用增强型电荷传输(BCT)电路替代传统开关电容技术流水线ADC中的高增益带宽积运放来实现电荷信号传输和余量处理,从而实现超低功耗。所提4.5位子级电路被运用于一款14位210 MS/s电荷域ADC中作为前端第1级子级电路,并在1P6M 0.18 μm CMOS工艺下实现。测试结果显示,该14位ADC电路在210 MS/s条件下对于30.1 MHz单音正弦输入信号得到的无杂散动态范围为85.4 dBc,信噪比为71.5 dBFS, ADC内核面积为3.2 mm2,功耗仅为205 mW。     

Expressions for bit error probability

The bit error probability (BEP) for many wireless communications networks can be expressed in the form R = Pr (X₂ < X₁) where X₁ and X₂ are independent random variables. Here, a comprehensive collection of formulas is derived for R by assuming the most commonly known models for X₁ and X₂. A discussion is provided of four possible applications to problems in wireless communications. Copyright © 2007 John Wiley & Sons, Ltd.