基于概率内存分配的内存安全研究

Some unsafe languages, like C and C+ + , let programmers maximize performance but are vulnerable to memory errors which can lead to program crashes and unpredictable behavior. Aiming to solve the problem, traditional memory allocating strategy is improved and a new probabilistic memory allocation technology is presented. By combining random memory allocating algorithm and virtual memory, memory errors are avoided in all probability during software executing. By replacing default memory allocator to manage allocation of heap memory, buffer overflows and dangling pointers are prevented. Experiments show it is better than Die-hard of the following aspects: memory errors prevention, performance in memory allocation set and ability of controlling working set. So probabilistic memory allocation is a valid memory errors prevention technology and it can tolerate memory errors and provide probabilistic memory safety effectively.     

嵌入式操作系统μC／OS-Ⅱ的一种内存管理算法

针对μc／OS-Ⅱ内存管理机制的不足,提出了一种新的内存管理算法．较小的内存分成固定大小的内存块,用位图索引组织;较大的内存用链表组织．实验表明,该方法能较好地提高内存分配速度和利用率,特别是对于内存块大小变化很大的系统．     

Reliability analysis and design of a fault-tolerant random access memory system

The design of a modular RAM system which is organized in a number of memory cards is examined. Two important factors are taken into account: the size of the memory chips used in a particular memory design, and the number of memory partitions which gives the maximum memory system reliability. Expressions are derived for three memory designs using two extreme failure models for the memory chips. These provide upper and lower bounds for the card and the entire memory system reliability, and allow the selection of an optimal configuration for a memory system which has a specified capacity and word length with (1) SEC or (2) SED-DED codes with spare memory cards.     

无线传感网络节点内存管理机制的研究与设计

针对现有无线传感器网络(Wireless Sensor Networks,WSNs)节点片上RAM（随机存储器）利用率低的特点,设计了一种基于链表的改进型内存管理方案。该方案以事件驱动开发模式为程序运行的前提,在将RAM划分为静态内存空间和动态内存空间之后,通过内存隔离技术,实现内存管理结构与内存空间在实体内存中的分离,从而达到提高节点内存利用率的目的。经测试,写内存的平均速率能够达到500kb/s,而在开启内存交换功能时,实际内存的使用率接近80%。最终为提高节点内存利用率提供了一种良好的解决方案。     

A content-addressable memory cell with MNOS transistors

Describes a new associative memory cell in which MNOS transistors are used as storage elements. The memory can perform functions as a read-only memory and at the same time as a read-write memory. The cell can be read as a random-access memory or as a content-addressable memory. As a CAM certain bits can be masked out, i.e., not compared with the stored bits. The comparison can also be controlled from the memory by the stored words. Since the word length or combinations of normal words can be stored in one word of the memory, fewer memory cells are needed than in an ordinary memory. Searches for groups of words (prime implicands) can be performed. Memory cells with an area of 5000-m- have been built to demonstrate the feasibility of the MNOS-CAM.     

Design and Realization of a Two-Level 64K Byte CCD Memory System for Microcomputer Applications

Charge coupled device (CCD) memory technology offers potential economic advantages over semiconductor random-access memory technology. However, the limitations incurred by the serial nature of CCD's have previously restricted their application to computer mainframe memories. The 64 kbyte CCD memory system described in this paper demonstrates the feasibility of CCD memory technology for moderate size memory systems applicable to microcomputer systems. Design objectives included low cost, adequate performance, reliable operation, small size, and low power consumption as well as simple interfacing to standard microprocessors. A simple two-level organization employing a random access memory (RAM) to buffer the serial CCD memory was used to improve the memory system performance and to simplify the interfacing of microcomputers. It is anticipated that the memory system can be easily modified to use 64 kbit and larger CCD memory devices as these become available. Furthermore, the memory system control logic could be integrated on a single large-scale integration (LSI) chip, thereby facilitating the fabrication of relatively large and economical memory systems with a low component count.     

Exploiting Memory Soft Redundancy for Joint Improvement of Error Tolerance and Access Efficiency

Technology roadmap projects nanoscale multibillion- transistor integration in the coming years. However, on-chip memory becomes increasingly exposed to the dual challenges of device-level reliability degradation and architecture-level performance gap. In this paper, we propose to exploit the inherent memory soft (transient) redundancy for on-chip memory design. Due to the mismatch between fixed cache line size and runtime variations in memory spatial locality, many irrelevant data are fetched into the memory thereby wasting memory spaces. The proposed soft-redundancy allocated memory detects and utilizes these memory spaces for jointly achieving efficient memory access and effective error control. A runtime reconfiguration scheme is also proposed to further enhance the soft-redundancy allocation. Simulation results demonstrate 74.8% average error-control coverage ratio on the SPEC CPU2000 benchmarks with average of 59.5% and 41.3% reduction in memory miss rate and bandwidth usage, respectively, as compared to the existing memory techniques. Furthermore, the proposed technique is fully scalable with respect to various memory configurations.      

Low-power memory mapping through reducing address bus activity

Arrays in behavioral specifications that are too large to fit into on-chip registers are usually mapped to off-chip memories during behavioral synthesis. We address the problem of system power reduction through transition count minimization on the memory address bus when these arrays are accessed from memory. We exploit regularity and spatial locality in the memory accesses and determine the mapping of behavioral array references to physical memory locations to minimize address bus transitions. We describe array mapping strategies for two important memory configurations: all behavioral arrays mapped to a single off-chip memory and arrays mapped into multiple memory modules drawn from a library. For the single memory configuration, we describe a heuristic for selecting a memory mapping scheme to achieve low power for each behavioral array. For mapping into a library of multiple memory modules, we formulate the problem as three logical-to-physical memory mapping subtasks and present experiments demonstrating the transition count reductions based on our approach. Our experiments on several image processing benchmarks show power savings of up to 63% through reduced transition activity on the memory address bus in the single memory case. We also observe a further transition count reduction by a factor of 1.5-6.7 over a straightforward mapping scheme in the multiple memories configuration     

基于动态调控的接入控制器内存调度策略

在网络流量较大的情况下,接入控制器对大量数据包进行处理的同时会造成内存调度频繁操作,并可能引起内存泄露以及大量内存碎片的产生,成为系统瓶颈所在.为了改善系统中的内存问题,介绍了接入控制器的整体构架以及内存分配的原理,并深入分析影响内存调度性能的因素,提出一种适合接入控制器的内存调度设计方案,并通过编程加以实现.通过池式内存的多种组合方式,采用高速算法将内存块灵活运用并加以监控,从而提高系统内存调度的整体性能,实现高效的上层应用开发.     

嵌入式多媒体应用中的片上存储器分配

为了提高嵌入式多媒体应用的运行速度并降低功耗,本文提出一种高效利用片上存储器的方法.将数据矩阵划分成合理大小的子块,分阶段地将数据子块转移到片上,并尽可能重复利用已经转移到片上的数据,以便有效地减少片外存储器与片上存储器之间的数据转移.通过对汇编语言中存储器阵操作数适当分配,避免读写数据延迟.根据汇编语言代码写出不产生流水线停滞的各个矩阵操作数的存储器位置限制条件,根据限制条件,本文提出求解矩阵分配的方法.     

基于对象引用关系的Java程序内存行为分析方法

本文提出一种基于对象引用关系的Java程序内存行为分析方法.与传统的通过内存消耗的大小来确定程序中数据结构的重要性并分析相关内存行为的方法不同,本文方法同时考虑内存消耗和内存支配两个因素来确定一个数据结构在程序内存行为中的重要性,通过研究数据结构之间在内存使用上的支配关系和对数据结构进行引用分析,得到程序中重要的内存行为.实验结果表明该方法能有效地分析程序的内存行为,且对比其它方法能提供更加准确的内存行为分析结果.     

MNOS-BORAM memory characteristics

This paper describes the characteristics of a block-oriented random-access memory (BORAM) system which uses a custom-designed 2-kbit MNOS memory array for information storage. Delivery of two fully functional memory systems has been a significant achievement in the development of the MNOS memory technology. The organizational concepts and performance characteristics of both the memory system and the MNOS memory array are discussed, including speed, data transfer rate, and retention.     

闪速存储器的研究与进展

介绍了闪速存储器的发展历史,分析了闪速存储器单元及电路的工作原理,并就“与非”结构闪速存储器进行探讨,最后讨论了在闪速存储器中应用的误差矫正码／电路和深亚微米（０．２５μｍ）闪速存储器技术。     

Flash存储器的冗余实现

Flash存储器是在20世纪80年代末逐渐发展起来的一种新型半导体非挥发性存储器,它具有结构简单、高密度、低成本、高可靠性和系统的电可擦除性等优点,是当今半导体存储器市场中发展最为迅速的一种存储器。文章对Flash存储器的发展现状及发展趋势进行了介绍,分析了Flash存储器的工作机理;并针对Flash存储器是一种数据正确性非理想的器件,在使用中可能会有坏损单元,探讨了Flash存储器冗余技术的种类和实现方法。     

确定性小世界特性记忆网络的建模与算法

为了形象直观的了解脑功能记忆小世界网络的形成及演化机制,采用复杂网络确定性建模的方法对记忆过程进行模拟,通过记忆节点及连边的抽取,建立符合记忆解剖特征和逻辑意义的连边机制.以集合为数据结构的建模算法仿真了小世界特性的记忆网络,同时数据元素的检索算法符合记忆特征.通过理论分析和数据仿真表明对脑功能记忆网络进行确定性建模是可行的.     

Nanotechnology enables a new memory growth model

As we enter the nanotechnology era, a big shift in paradigm comes to the memory industry. The traditional computer industry for dynamic RAM is expected to mature its memory-bit consumption with a relatively low growth rate. Meanwhile, the memory consumption and high-density memory usage in mobile handsets and digital consumer applications will grow very fast. For these new applications, NAND Flash memory will be the key enabling technology and its easy scaling and multibit/cell capabilities require a new memory growth model. The well-known Moore's law still holds for most cases after the quarter-century history of the integrated circuit industry. However, the paradigm shift in the memory industry requires a new memory growth model: "a twofold increase per year in memory density." This paper will cover some details of recent memory technologies, application trends, and the proposed new memory growth model.     

网络存储器的设计

针对计算机系统中磁盘的I／O性能问题,对比各种解决这一问题的方法,提出了网络存储器设计的方法,网络存储器是通过提高处理器与存储器之间的数据交换的速度来提高计算机系统性能的。通过对网络存储器的工作时间的分析证实了网络存储器设计的可行性,并提出三种网络存储器的设计方法。     

System-level impacts of persistent main memory using a search engine

Computer memory systems traditionally use distinct technologies for different hierarchy levels, typically volatile, high speed, high cost/byte solid state memory for caches and main memory (SRAM and DRAM), and non-volatile, low speed, low cost/byte technologies (magnetic disks and flash) for secondary storage. Currently, non-volatile memory (NVM) technologies are emerging and may substantially change the landscape of memory systems. In this work we assess system-level latency and energy impacts of a computer with persistent main memory using PCRAM and Memristor, comparing the development and execution of a search engine application implementing both a traditional file-based approach and a memory persistence approach (Mnemosyne). Our observations show that using memory persistence on top of NVM main memory, instead of a file-based approach on top DRAM/Disk, produces less than half lines of code, is more than 4× faster to develop, consumes 33× less memory energy, and executes search tasks up to 33× faster.     

Automatic generation and compaction of March tests for memoryarrays

Given a set of memory array faults, the problem of computing a compact March test that detects all specified memory array faults is addressed. In this paper, we propose a novel approach in which every memory array fault is modeled by a set of primitive memory faults. A primitive March test is defined for each primitive memory fault. We show that March tests that detect the specified memory array faults are composed of primitive March tests. A method to compact the March tests for the specified memory array faults is described. A set of examples to illustrate the approach is presented. Experimental results demonstrate the productivity gained using the proposed framework     

An Organic-Based Diode–Memory Device With Rectifying Property for Crossbar Memory Array Applications

An organic-based diode–memory device that has a bistable memory function and a high rectification ratio has been studied. The diode–memory device is fabricated by incorporating an organic-based diode component in series with a polymer memory component. The organic-based diode–memory device performs well as a reliable rectifying memory device, achieving an excellent on/off current ratio of $ hbox{10}^{6}$ and a high rectification ratio of $hbox{10}^{3}$ . The conduction models are also fitted to study the proposed conductivity mechanism of the rectifying memory device. The demonstrated organic-based diode–memory device is very promising for use in a passive matrix crossbar polymer memory array.