Substrate Noise Simulation Techniques for Analog-Digital Mixed LSI Design

Crosstalk from digital to analog circuits can be causative of operation fails in analog-digital mixed LSIs. This paper describes modeling techniques and simulation strategies of the substrate coupling noise. A macroscopic substrate noise model that expresses the noise as a function of logic state transition frequencies among digital blocks is proposed. A simulation system based on the model is implemented in the mixed signal simulation environment, where performance degradation of the 2nd order ADC coupled to digital noise sources is clearly simulated. These results indicate that the proposed behavioral modeling approach allows practicable full chip substrate noise simulation measures.     

Fast Substrate Noise Aware Floorplanning for Mixed Signal SOC Designs

In this paper, we introduce a novel substrate noise estimation technique during early floorplanning for mixed signal system-on-chip (SOC), based on block preference directed graph (BPDG). Given a set of analog and digital blocks, BPDG is constructed based on their inherent noise characteristics to capture the preferred relative locations for substrate noise minimization. For each instance of floorplan in sequence pair or ${B}^{ast}$-tree, we efficiently count the number of violations against BPDG which correlates remarkably well with accurate but computation-intensive substrate noise modeling. Thus, our BPDG-based model can guide fast substrate noise-aware floorplanning and layout optimization for mixed signal SOC. Our experimental results show that the proposed approach is significantly faster than conventional full-blown substrate model-based floorplanning.      

一种CMOS混合信号电路衬底噪声耦合模型

利用二维器件模拟器MEDICI提取出重掺杂外延型衬底的电阻宏简化模型,所需的6个参数均可通过器件模拟得到,能够精确表征混合信号集成电路中的衬底噪声特性。基于0.25μm CMOS工艺所建立的电阻宏模型,设计了简单的混合信号电路进行应用验证,证明了该模型能够有效表征混合信号集成电路的衬底噪声。     

A new and efficient approach for estimating the accurate time-domain response of single and capacitive coupled distributed RC interconnects

This paper describes a novel yet highly efficient approach for estimating the time-domain response of capacitive coupled distributed RC interconnects. By using this method, the voltage signal at any particular point in such wires can be accurately and quickly obtained with very low computational cost. The proposed model exhibits a very good agreement with HSPICE simulations with worst-case error less than 3% and can be readily implemented in CAD analysis tools. This paper also presents an efficient model to estimate the capacitive crosstalk in high-speed very large scale integration (VLSI) circuits. Experimental results show that the maximum error of our peak noise predictions is less than 2.5%. In addition, this work presents an efficient artificial neural network (ANN)-based technique for modeling the time-domain response of interconnects and crosstalk noise. While existing fast noise estimation metrics may overestimate or underestimate the coupling noise, the simulation results demonstrate the ability of this approach to successfully predict coupling noise with a very good accuracy as compared to HSPICE in modest CPU times. Thereby, the proposed models and techniques can be used to predict the signal integrity for designing high-speed and high-density VLSI circuits.     

Substrate model extraction using finite differences and parallel multigrid

Substrate noise in integrated circuits is one of the most important problems in high-frequency mixed-signal designs, such as communication, biomedical and analog signal processing circuits and systems. Fast-switching digital blocks inject noise into the common substrate, hindering the performance of high-precision sensible analog circuitry. Miniaturization trends require increasing the accuracy in substrate coupling simulation environments. However, model extraction and evaluation times should not increase, which demands for fast and still accurate substrate model extraction tools.

In this work, a three-dimensional finite difference extraction methodology is presented. The resulting three-dimensional mesh is efficiently reduced to a circuit-level contact-based model by means of a fast multigrid-based algorithm. Moreover, this contact-based model extraction is shown to be efficiently computed in a parallel environment, resulting in extremely useful extraction speedups. Extraction results prove the proposed method to be very efficient, providing linear time and space complexity, and a constant number of iterations, outperforming competing algorithms.     

Analysis of the PLL jitter due to power/ground and substrate noise

Phase-locked loops (PLL) in radio-frequency (RF) and mixed analog-digital integrated circuits (ICs) experience substrate coupling due to the simultaneous circuit switching and power/ground (P/G) noise which translate to a timing jitter. In this paper. an analysis of the PLL timing jitter due to substrate noise resulting from P/G noise and large-signal switching is presented. A general comprehensive stochastic model of the substrate and P/G noise sources in very large-scale integration (VLSI) circuits is proposed. This is followed by calculation of the phase noise of the constituent voltage-controlled oscillator (VCO) in terms of the statistical properties of substrate and P/G noise. The PLL timing jitter is then predicted in response to the VCO phase noise. Our mathematical method is utilized to study the jitter-induced P/G noise in a CMOS PLL, which is designed and simulated in a 0.25-/spl mu/m standard CMOS process. A comparison between the results obtained by our mathematical model and those obtained by HSPICE simulation prove the accuracy of the predicted model.     

Dielectric Resonator Antenna on Silicon Substrate for System On-Chip Applications

This paper presents for the first time the design and performance of a novel integrated dielectric resonator antenna fabricated on a high conducting silicon substrate for system on-chip applications. A differential launcher to excite the ${rm TE}_{01delta}$ mode of the high permittivity cylindrical dielectric resonator was fabricated using the IBM SiGeHP5 process. The proposed antenna integrated on a silicon substrate of conductivity 7.41 S/m has an impedance bandwidth of 2725 MHz at 27.78 GHz, while the achieved gain and radiation efficiency are 1 dBi and 45% respectively. The design parameters were optimized employing Ansoft HFSS simulation software. Very good agreement has been observed between simulation and experimental results. The results demonstrate that integration of dielectric resonator antennas on silicon is viable, leading to the fabrication of high efficient RF circuits, ultra miniaturization of ICs and for the possible integration of active devices.      

A single-lead ECG enhancement algorithm using a regularized data-driven filter

We presented a novel way of deriving a subspace filter for enhancing a noisy electrocardiogram (ECG) signal contaminated by electromyogram (EMG). The new subspace filter was based on a multiple cycle prediction (MCP) modeling of a single-lead ECG. The adoption of an MCP model resulted in a data matrix more suitable for separating noise and signal subspaces than the linear prediction (LP) model that is implicitly assumed in many existing subspace filters. Alignment of ECG cycles of different length is required for MCP modeling and was handled by a dynamic time warping (DTW) algorithm. A run-time procedure was designed for automatically determining the signal space dimension adaptively. To validate the new filter in a quantitative way, 12 clean realistic ECG segments with different degrees of heart rate variability generated using the ECGSyn program were mixed with different realizations of EMG noise in the MIT-BIH Noise Stress Test Database and locally acquired EMG at a typical 10-dB signal-to-noise ratio. The performance of the proposed method was compared to three existing ECG enhancement algorithms and achieved encouraging results. In addition, various ECG recordings from MIT-Arrythmia database were also mixed with EMG noise and subjected to the same four filters resulting in a qualitative comparison of them.     

A New Lossy Substrate Model for Accurate RF CMOS Noise Extraction and Simulation With Frequency and Bias Dependence

A lossy substrate model is developed to accurately simulate the measured RF noise of 80-nm super-100-GHz f_T n-MOSFETs. A substrate RLC network built in the model plays a key role responsible for the nonlinear frequency response of noise in 1-18-GHz regime, which did not follow the typical thermal noise theory. Good match with the measured S-parameters, Y-parameters, and noise parameters before deembedding proves the lossy substrate model. The intrinsic RF noise can be extracted easily and precisely by the lossy substrate deembedding using circuit simulation. The accuracy has been justified by good agreement in terms of I_d,g_m, Y-parameters, and f _T under a wide range of bias conditions and operating frequencies. Both channel thermal noise and resistance induced excess noises have been implemented in simulation. A white noise gamma factor extracted to be higher than 2/3 accounts for the velocity saturation and channel length modulation effects. The extracted intrinsic NF_min as low as 0.6-0.7 dB at 10 GHz indicates the advantages of super-100 GHz f_T offered by the sub-100-nm multifinger n-MOSFETs. The frequency dependence of noise resistance R_n suggests the bulk RC coupling induced excess channel thermal noise apparent in 1-10-GHz regime. The study provides useful guideline for low noise and low power design by using sub-100-nm RF CMOS technology     

基于SIMULINK的开关型∑-△调制器行为级建模

为精确反映多种非理想因素对开关型∑-△调制器的影响,提高其在SIMULINK仿真器下的仿真精度,针对SIMULINK的行为级建模提出一种新的积分器模型.主要的改进之处包括:在运放模块中引入了有关直流增益非线性及信号建立过程非理想性的考虑,在开关模块中引入了电荷注入效应和导通阻抗的信号相关性影响,并将噪声模型作为独立模块引入系统.应用该模型进行SIMULINK仿真,并与TSMC 0.35μm混合信号工艺下SPICE仿真结果进行比较验证.结果表明,所提出的模型成功地反映了上述因素对电路的重要影响,模型的应用提高了SIMULINK的仿真精度.     

多层封装基板中同步开关噪声研究

文章以栅格阵列封装(land grid array,LGA)模型为研究对象,分析了多层封装基板中的同步开关噪声(simultaneous switching noise,SSN)问题。首先利用频域仿真工具PowerSI得到了键合线和信号布线的S参数模型。然后通过在电路仿真工具HSPICE中加载封装结构的S参数模型和驱动器模型来仿真同步开关噪声。最后在设计中选取在多层基板上添加去耦电容的方式来减小同步开关噪声。仿真结果表明,通过在本LGA多层基板设计中添加110pF容值的去耦电容,可以较好地减少同步开关噪声,满足设计要求。     

X-Band Substrate Integrated Waveguide Amplifier

Design and realization of a compact X-band single-transistor amplifier with substrate integrated waveguide (SIW)-based input and output matching networks is presented. The overall size of the proposed SIW amplifier is only $1.5lambda_{rm g}$ at the center frequency. Using a calibration technique, we extract the $S$ -parameters of the fabricated amplifier with reference to its SIW ports. Measurements show that the amplifier features 10 dB of power gain with less than 2 dB of ripple and more than 10 dB of input and output return losses on the SIW ports in the entire frequency band. Due to an appropriate modeling of the constituent blocks of the amplifier, a good agreement between the simulation and measurement results is observed.      

MOSFET衬底电流模型及参数提取

在短沟道ＭＯＳＦＥＴ器件物理的基础上,导出了其衬底电流解析模型,并通过实验进行了模型参数提取。模型输出与短沟ＭＯＳＦＥＴ实测结果比较接近,可应用于ＶＬＳＩ／ＵＬＳＩ可靠性模拟与监测研究和亚微米ＣＭＯＳ电路设计。     

Substrate Noise Coupling in SoC Design: Modeling, Avoidance, and Validation

Issues related to substrate noise in system-on-chip design are described including the physical phenomena responsible for its creation, coupling transmission mechanisms and media, parameters affecting coupling strength, and its impact on mixed-signal integrated circuits. Design guidelines and best practices to minimize the generation, transmission, and reception of substrate noise are outlined, and different modeling approaches and computer simulation methods used in quantifying the noise coupling phenomena are presented. Finally, experiments that validate the modeling approaches and mitigation techniques are reviewed     

Compact MOS Implementation of a Reaction-Diffusion CNN

A biologically inspired single layer cellular neural network (CNN) with trigger wave formation capability is presented. A novel compact MOS cell circuit is proposed which exhibits a third order I-V characteristic with negative differential resistance (NDR). Certain D.C. characteristics of both the proposed cell and the network are described and corresponding theoretical estimations are presented. It is shown that the CNN formed by resistive coupling of these cells has very low complexity and realizes a reaction-diffusion system. The dynamical network behavior is demonstrated by transient simulations of a 2D cell array at the circuit level.Koray Karahalilolu received the B.Sc., M.Sc., and Ph.D. degrees in electrical engineering from Boaziçi University, Istanbul, Turkey, in 1993, 1996, and 2002, respectively.Currently he is a Research Assistant Professor with the Department of Electrical Engineering, University of Nebraska, Lincoln. He also worked as a teaching assistant with the Department of Electrical and Electronics Engineering at Boaziçi University.His research interests include VLSI neural networks, device modeling and simulation, analog circuits and systems, and nanodevice system applications.Sina Balkr received the B.S. degree in electrical engineering from Boaziçi University, Istanbul, Turkey, in 1987, and the M.S. and Ph.D. degrees in electrical engineering from Northwestern University, Evanston, IL, in 1989 and 1992, respectively.Between August 1992 and August 1998, he was with the Department of Electrical and Electronics Engineering, Boaziçi University, as an Assistant and Associate Professor. Currently, he is with the Department of Electrical Engineering, University of Nebraska-Lincoln. His research interests include CAD of VLSI systems, analog VLSI design automation, and focal-plane computation arrays for image processing.     

基于Matlab/Simulink(Stateflow) 的模/ 数混合信号系统 的精准行为模拟

详细且完整地介绍了在Matlab/Simulink（Stateflow）环境中对模/数混合信号系统的精准行为模拟及仿真。利用双斜率模/数转换器（Dual-slopeADC）作为模拟对象,在分析了转换器的结构、工作原理、系统中重要的非理想性（例如运放及比较器的输入参考噪音及电压偏移等）以及它们对系统的工作性能的影响的基础上,设计实现了系统的Matlab/Simulink（State-flow）行为模型并对其进行了仿真验证。     

The CHIP - A Design Guide for Reducing Substrate Noise Coupling in RF Applications

This article discusses a set of design guidelines to reduce the on-chip substrate noise coupling in RF and mixed signal applications. Measurement data is presented to compare the various signal isolation techniques. A design flow is calibrated to the measured data and is used to expand the design guide to include the effects of the geometrical and electrical parameters of the isolation structures as well as the frequency of operation on the isolation level. A set of guidelines is presented to the reader as a summary of the studied experiments     

Noise considerations for mixed‐signal RF IC transceivers

This paper discusses design tradeoffs for mixedsignal radio frequency integrated circuit (RF IC) transceivers for wireless applications in terms of noise, signal power, receiver linearity, and gain. During air wave transmission, the signal is corrupted by channel noise, adjacent interfering users, image signals, and multipath fading. Furthermore, the receiver corrupts the incoming signal due to RF circuit nonlinearity (intermodulation), electronic device noise, and digital switching noise. This tutorial paper gives an overview of the design tradeoffs needed to minimize RF noise in an integrated wireless transceiver. Fundamental device noise and the coupling of switching noise from digital circuits to sensitive analog sections and their impact on RF circuits such as frequency synthesizers are examined. Methods to minimize mixedsignal noise coupling and to model substrate noise effects are presented.     

A novel pulse swallow based frequency divider circuit for a phase-locked loops

In this paper, an analysis of the memory effect in two amplifier-shared switched-capacitor integrators for a discrete-time sigma-delta (\(\varSigma \varDelta\)) modulator is presented. Interaction between the integrators is modeled by feeding an integrator output voltage to another integrator input and vice versa and multiplying by a coefficient depending on DC gain and input parasitic capacitance of the opamp. The model is applied to a second-order \(\varSigma \varDelta\) modulator to analyze how signal and noise transfer functions are altered. The analysis reveals that the magnitude response of the signal transfer function is minimally affected in the low-frequency signal band, whereas that of the noise transfer function can be increased significantly in the signal band, degrading the effectiveness of noise shaping. In relation to the parasitic capacitance at the opamp input, the DC gain required of the opamp is derived quantitatively for a given degradation of modulator dynamic range with respect to different oversampling ratios. Considering leaky integration, which is also caused by the finite opamp DC gain, the DC gain requirement imposed by the memory effect is proved to be more severe than that by leaky integration. Macromodel-based circuit simulation results confirm the accuracy of the proposed model and equations.     

Adaptive nonlinear filters for narrow-band interference suppressionin spread-spectrum CDMA systems

This paper presents a novel nonlinear filter and parameter estimator for narrow band interference suppression in code division multiple access spread-spectrum systems. As in the article by Rusch and Poor (1994), the received sampled signal is modeled as the sum of the spread-spectrum signal (modeled as a finite state independently identically distributed (i.i.d.) process-here we generalize to a finite state Markov chain), narrow-band interference (modeled as a Gaussian autoregressive process), and observation noise (modeled as a zero-mean white Gaussian process). The proposed algorithm combines a recursive hidden Markov model (HMM) estimator, Kalman filter (KF), and the recursive expectation maximization algorithm. The nonlinear filtering techniques for narrow-band interference suppression presented in Rusch and Poor and our proposed HMM-KF algorithm have the same computational cost. Detailed simulation studies show that the HMM-KF algorithm outperforms the filtering techniques in Rusch and Poor. In particular, significant improvements in the bit error rate and signal-to-noise ratio (SNR) enhancement are obtained in low to medium SNR. Furthermore, in simulation studies we investigate the effect on the performance of the HMM-KF and the approximate conditional mean (ACM) filter in the paper by Rusch and Poor, when the observation noise variance is increased. As expected, the performance of the HMM-KF and ACM algorithms worsen with increasing observation noise and number of users. However, HMM-KF significantly outperforms ACM in medium to high observation noise