一种面向SOC的衬底噪声宏模型

针对SOC中常见的衬底噪声耦合问题,通过将器件模拟与拟合法相结合,基于0.25 μ m CMOS工艺提取衬底结构参数建立了电阻宏模型.该模型被应用于CMOS放大器电路,利用Hspice进行仿真,仿真结果表明,该模型从时、频域角度都能较好地表征出衬底噪声对模拟电路性能的影响,对深亚微米混合信号电路设计具有重要的指导意义.     

重掺杂型混合信号集成电路衬底的噪声模型研究

应用器件模拟软件SILVACO模拟三种结构重掺杂型衬底中注入高频电流的分布,根据模拟结果分析得出重掺杂型衬底的简化模型为一单节点,进而将简化模型与实际的混合信号集成电路结合,建立起重掺杂型衬底的噪声模型,并给出了参数估算式。     

数模混合电路衬底耦合模型研究

提出了数模混合集成电路衬底耦合噪声的一种建模方案将集成电路芯片的衬底划分为多个Voronoi图,计算各区域的R、C值,在将衬底RC网络映射到原电路网表之后,对新网表进行SPICE模拟,分析数模混合集成电路中的衬底噪声.用此模型模拟了两个数模混合集成电路的衬底耦合噪声,指出了在模拟电路关键器件周围加保护环是减少衬底耦合噪声的一种有效途径.     

混合信号集成电路的衬底耦合噪声分析

本文系统分析了混合信号集成电路的衬底噪声耦合的研究进展.简要分析了衬底噪声的基本机理,及其对混合信号电路的影响,在此基础上分析比较了目前已提出的几种主要的衬底耦合噪声模型.通过分析不同类型衬底内的噪声耦合,介绍了一些电路设计中的去耦方法.最后讨论了衬底耦合噪声研究的发展方向.     

一种混合信号集成电路衬底耦合噪声分析方法

讨论分析了混合信号集成电路衬底噪声耦合的机理,及对模拟电路性能的影响。提出了一种混合信号集成电路衬底耦合噪声分析方法,基于TSMC 0.35μm 2P4M CMOS工艺,以14位高速电流舵D/A转换器为例,给出了混合信号集成电路衬底耦合噪声分析方法的仿真结果,并与实际测试结果进行比较,证实了分析方法的可信性。     

混合信号SoC中的衬底噪声耦合效应

衬底噪声耦合是深亚微米混合信号集成电路中常见的噪声干扰效应,严重地影响了模拟电路的性能。系统地阐述混合信号SoC中的衬底噪声耦合效应及其研究现状,讨论利用基于格林方程的边界元法对衬底建模的方法,并且分别从工艺、版图、电路等不同层次衬底噪声耦合效应的抑制方法与技术,同时对将来衬底噪声研究的发展方向以及新思路进行分析与讨论。     

深亚微米CMOS混合信号电路衬底噪声耦合宏模型

提出了一种基于二维器件模拟的深亚微米工艺外延型衬底的电阻宏模型.该宏模型通过器件模拟与非线性拟合相结合的方法建立,使衬底寄生参数的提取更加方便,同时保障了深亚微米电路特性的模拟精度.此外,该宏模型结构简单,可以得到与器件模拟基本一致的模拟结果,并可以方便地嵌入SPICE中进行一定规模的电路模拟.     

CMOS混合信号集成电路中的串扰效应

论述了混合信号集成电路中的串扰效应及其对电路本身的影响,重点讨论了在重掺杂衬底中数字干扰对模拟器件的影响,并给出了数字噪声注入等效电路.同时从制造工艺和设计技术方面讨论了降低串扰效应的方法.     

混合信号电路的衬底电阻网络模型

通过等效电路数值提取方法，提出了衬底电阻网络模型，该模型具有清晰的物理意义，可获得很好的精度，有利于混合信号电路衬底耦合效应的模拟。将该模型应用于规则和不规则区域的电阻值提取，用Hspice电路模拟器对电阻网络进行模拟，与Medici器件模拟器模拟结果和解析公式结果进行比较，证明了该模型的准确性。     

基于混合宏模型的无电容型LDO设计

模拟集成电路的"自顶向下"设计方法能大大提高电路设计效率.提出了一种"混合宏模型",能高效、简便地完成模拟集成电路的建模,进而指导器件级电路设计.基于"混合宏模型"的设计方法,完成了一款基于HHNEC 0.25 μm标准CMOS工艺的无电容型LDO设计.     

A New Lossy Substrate Model for Accurate RF CMOS Noise Extraction and Simulation With Frequency and Bias Dependence

A lossy substrate model is developed to accurately simulate the measured RF noise of 80-nm super-100-GHz f_T n-MOSFETs. A substrate RLC network built in the model plays a key role responsible for the nonlinear frequency response of noise in 1-18-GHz regime, which did not follow the typical thermal noise theory. Good match with the measured S-parameters, Y-parameters, and noise parameters before deembedding proves the lossy substrate model. The intrinsic RF noise can be extracted easily and precisely by the lossy substrate deembedding using circuit simulation. The accuracy has been justified by good agreement in terms of I_d,g_m, Y-parameters, and f _T under a wide range of bias conditions and operating frequencies. Both channel thermal noise and resistance induced excess noises have been implemented in simulation. A white noise gamma factor extracted to be higher than 2/3 accounts for the velocity saturation and channel length modulation effects. The extracted intrinsic NF_min as low as 0.6-0.7 dB at 10 GHz indicates the advantages of super-100 GHz f_T offered by the sub-100-nm multifinger n-MOSFETs. The frequency dependence of noise resistance R_n suggests the bulk RC coupling induced excess channel thermal noise apparent in 1-10-GHz regime. The study provides useful guideline for low noise and low power design by using sub-100-nm RF CMOS technology     

A scalable substrate noise coupling model for design ofmixed-signal IC's

This paper describes a design-oriented scalable macromodel for substrate noise coupling in heavily-doped substrates. The model requires only four parameters which can be readily extracted from a small number of device simulations or measurements. Once these parameters have been determined, the model can be used in design for any spacing between the injection and sensing contacts and for different contact geometries. The scalability of the model with separation and width provides insight into substrate coupling and optimization issues prior to and during the layout phase. The model is validated with measurements from test structures fabricated in a 0.5 μm CMOS process. Applications of the model to circuit design are demonstrated with simulation results     

SWAN: high-level simulation methodology for digital substrate noise generation

Substrate noise generated by the switching digital circuits degrades the performance of analog circuits embedded on the same substrate. It is therefore important to know the amount of noise at a certain point on the substrate. Existing transistor-level simulation approaches based on a substrate model extracted from layout information are not feasible for digital circuits of practical size. This paper presents a complete high-level methodology, which simulates a large digital standard cell-based design using a network of substrate macromodels, with one macromodel for each standard cell. Such macromodels can be constructed for both EPI-type and bulk-type substrates. Comparison of our substrate waveform analysis (SWAN) to several measurements and to several full SPICE simulations indicates that the substrate noise is simulated with our methodology within 10%-20% error in the time domain and within 2 dB relative error at the major resonance in the frequency domain. However, it is several orders of magnitude faster in CPU time than a full SPICE simulation.     

AC Modeling of the ggNMOS ESD Protection Device

From AC analysis results utilizing a 2‐dimensional device simulator, we extracted an AC‐equivalent circuit of a grounded‐gate NMOS (ggNMOS) electrostatic discharge (ESD) protection device. The extracted equivalent circuit is utilized to analyze the effects of the parasitics in a ggNMOS protection device on the characteristics of a low noise amplifier (LNA). We have shown that the effects of the parasitics can appear exaggerated for an impedance matching aspect and that the noise contribution of the parasitic resistances cannot be counted if the ggNMOS protection device is modeled by a single capacitor, as in prior publications. We have confirmed that the major changes in the characteristics of an LNA when connecting an NMOS protection device at the input are reduction of the power gain and degradation of the noise performance. We have also shown that the performance degradation worsens as the substrate resistance is reduced, which could not be detected if a single capacitor model is used.     

A comparison by simulation and by measurement of the substrate noise generated by CMOS, CSL, and CBL digital circuits

Current-steering logic (CSL) and current-balanced logic (CBL) are logic families that have been proposed with the objective of reducing the substrate noise in mixed-signal integrated circuits. These two families are compared here with conventional CMOS by simulation, using a substrate model extracted from the layouts, and also by measurements on a test chip. With small, low-power cells, noise reduction of CSL and CBL with respect to CMOS is only marginal; the same result is obtained with large, high-power (buffer) cells, if the supply wire inductance is very low. For large cells with typical wire bonding supply inductance (of the order of 10 nH), CBL cells provide significant noise reduction and are more effective than CSL cells; these become even noisier than CMOS cells for large inductance values. The results here, considering the real substrate noise, are more reliable than previous evaluations considering only the amplitude of the supply current spikes.     

Substrate noise generation in complex digital systems: efficient modeling and simulation methodology and experimental verification

More and more system-on-chip designs require the integration of analog circuits on large digital chips and will therefore suffer from substrate noise coupling. To investigate the impact of substrate noise on analog circuits, information is needed about digital substrate noise generation. In this paper, a recently proposed simulation methodology to estimate the time-domain waveform of the substrate noise is applied to an 86-Kgate CMOS ASIC on a low-ohmic epi-type substrate. These simulation results have been compared with substrate noise measurements on this ASIC and the difference between the simulated and measured substrate noise rms voltage is less than 10%. The simulated time domain waveform and frequency spectrum of the substrate noise correspond well with the measurements, indicating the validity of this simulation methodology. Both measurements and simulations have been used to analyze the substrate noise generation in more detail. It has been found that direct noise coupling from the on-chip power supply to the substrate dominates the substrate noise generation and that more than 80% of the substrate noise is generated by simultaneous switching of the core cells. By varying the parameters of the simulation model, it has been concluded that a flip-chip packaging technique can reduce the substrate noise rms voltage by two orders of magnitude when compared to traditional wirebonding.     

Measuring and modeling the effects of substrate noise on the LNAfor a CMOS GPS receiver

The influence of substrate noise coupling on the performance of a low-noise amplifier (LNA) for a CMOS GPS receiver has been investigated both analytically and experimentally. A frequency-domain approach has been used to model both noise injection into the substrate from digital circuitry integrated on the same chip and the mechanisms by which that noise can affect analog circuit behavior. The results of this study reveal that substrate noise can modulate the LNA input signal as well as couple directly to the amplifier's output     

A new lossy substrate de-embedding method for sub-100 nm RF CMOS noise extraction and modeling

A new equivalent circuit method is proposed in this paper to de-embed the lossy substrate and lossy pads' parasitics from the measured RF noise of multifinger MOSFETs with aggressive gate length scaling down to 80 nm. A new RLC network model is subsequently developed to simulate the lossy substrate and lossy pad effect. Good agreement has been realized between the measurement and simulation in terms of S-parameters and four noise parameters, NF/sub min/ (minimum noise figure), R/sub n/ (noise resistance), Re(Y/sub sopt/), and Im(Y/sub sopt/) for the sub-100-nm RF nMOS devices. The intrinsic NF/sub min/ extracted by the new de-embedding method reveal that NF/sub min/ at 10 GHz can be suppressed to below 0.8 dB for the 80-nm nMOS attributed to the advancement of f/sub T/ to 100-GHz level and the effectively reduced gate resistance by multifinger structure.     

Analysis and experimental verification of digital substrate noisegeneration for epi-type substrates

Substrate coupling in mixed-signal IC's can cause important performance degradation of the analog circuits. Accurate simulation is therefore needed to investigate the generation, propagation, and impact of substrate noise. Recent studies were limited to the time-domain behavior of generated substrate noise and to noise injection from a single noise source. This paper focuses on substrate noise generation by digital circuits and on the spectral content of this noise. To simulate the noise generation, a SPICE substrate model for heavily doped epi-type substrates has been used. The accuracy of this model has been verified with measurements of substrate noise, using a wide-band, continuous-time substrate noise sensor, which allows accurate measurement of the spectral content of substrate noise. The substrate noise generation of digital circuits is analyzed, both in the time and frequency domain, and the influence of the different substrate noise coupling mechanisms is demonstrated. It is shown that substrate noise voltages up to 20 mV are generated and that, in the frequency band up to 1 GHz, noise peaks are generated at multiples of the clock and repetition frequency. These noise signals will strongly deteriorate the behavior of small signal analog amplifiers, as used in integrated front-ends     

Comprehensive Electromagnetic Modeling of On-Chip Switching Noise Generation and Coupling

A comprehensive modeling methodology is presented for the investigation of on-chip noise generation and coupling due to power switching. The backbone of the methodology is an electromagnetic model for the on-chip portion of the power grid. This allows for the impact of the displacement current density and, hence, electromagnetic retardation, to be taken into account in the accurate modeling of the power grid behavior at picosecond switching speeds. In this manner, and through the interfacing of this model with an electromagnetic model for the package portion of the power grid, which is described in terms of a multiport rational matrix transfer function, the impact of package-chip electrical interactions on switching noise can be modeled with electromagnetic accuracy. The electromagnetic model for the power grid is complemented by a resistance-capacitance model for the semiconductor substrate, which is capable of modeling local substrate induced noise coupling between neighboring circuits. Finally, distributed resistance, inductance, capacitance and conductance circuits for signal wires are extracted and used to provide for a transmission line-based modeling of crosstalk and power grid induced signal degradation. Transient simulations using the proposed comprehensive model are carried out using a hybrid time-domain integration scheme which combines a SPICE-like engine for the analysis of all circuit netlists and the nonlinear drivers incorporated in the model with a numerical integration algorithm suitable for the expedient update of the state variables in the discrete electromagnetic model for the power grid.