InSb红外探测器钝化前清洗工艺研究

对InSb红外探测器钝化前清洗工艺进行了研究。在传统清洗方法的基础上增加专用清洗液进行清洗,以优化钝化前InSb材料的表面质量。飞行时间二次离子质谱仪(Time-of-Flight Secondary Ion Mass Spectrometry, TOF-SIMS)质谱检测表明,增加专用清洗液清洗工艺后,InSb材料表面的Si杂质浓度降低了约85%,主要有机物杂质浓度降幅约为30%~60%,表面整体杂质含量显著降低。经流片验证,增加专用清洗液进行钝化前表面清洗,I-V性能更优,InSb光伏芯片的长期可靠性显著提高。这说明钝化前InSb材料的表面质量对InSb红外探测器的性能和可靠性具有重要影响。本文提供的钝化前清洗优化方向具有一定的指导意义。     

开管充气扩散法制备InSbp-n结

本文报道用开管充气扩散法制备InSb的p-n结,使探测器的零偏压阻抗和探测率得到很大的提高。结合采用表面钝化技术后,器件的反向击穿电压也大大提高,单元器件的边缘效应和多元列阵的串音问题也得到较彻底的解决。现已用此工艺制造出高性能的单元、64元InSb列阵器件及10元TDI和20元多路传输红外COD。     

抑制In元素在CdTe中的退火扩散

分子束外延HgCdTe/InSb 材料需要阻止 In 元素在 HgCdTe 中的不受控扩散。我们使用 CdTe缓冲层作为阻挡层,以期控制 In 的扩散。为研究 In 元素在 CdTe 材料中的扩散,我们使用分子束外延方法获得CdTe/InSb样品。考虑到在退火时In 元素可能通过环境扩散污染材料,我们使用 SiO2 作为钝化层,通过对比试验发现 In 元素通过环境扩散污染表面的证据,为控制 In 元素的扩散提供新的思路。     

表面预处理对InSb钝化层界面的影响

本文介绍了采用不同的方法对InSb表面进行表面预处理,来改善InSb钝化膜层的电学性能。通过对InSb MIS结构进行C-V测试来评价不同方法预处理制备的钝化结构的电学特性。结果表明等离子预处理能明显改善InSb衬底和钝化层之间的界面性能,尤其是选用N2O等离子预处理InSb衬底表面,在控制界面陷阱和减少钝化层固定电荷方面,效果更明显,有利于提高InSb红外器件的可靠性。     

InSb红外焦平面探测器十字盲元问题的研究

InSb红外焦平面探测器在中波红外波段占据重要地位,但十字盲元问题严重降低了探测器的性能。通过聚焦离子束定位剥离手段,发现了十字盲元区域的铟凸点失效。进一步检测发现,铟凸点制备参数欠佳。通过改进铟凸点形状和增加高度,加强了焊接面的牢固度。此后发现极少InSb器件存在十字盲元问题。在80℃下对铟凸点改进后的InSb红外器件进行了14天烘烤。经测试,十字盲元数目保持不变,铟凸点的可靠性较好。改进铟凸点制备技术可有效解决十字盲元问题。互连失效是十字盲元问题的主要原因。以此类推,该方法可解决所有InSb红外器件的十字盲元问题。     

光伏型锑化铟多元红外探测器

本文简要介绍用箱法扩散成结,蒸发SiO_2钝化表面和金属化层作欧姆接触,热压焊等类似Si集成电路工艺研制的InSb多元红外探测器的情况,获得了高阻抗、无串扰的线列器件。并就工艺对串扰和均匀性的影响进行讨论。     

MBE外延InSb基CdTe工艺研究

成功制备了CdTe/InSb复合衬底,为长波HgCdTe外延提供了可能。通过工艺研究解决了InSb氧化层去除及In元素扩散控制两个难点问题,使用As钝化法可以解决双腔衬底转移的问题,在常用的退火工艺下,通过厚度的调整可以阻挡In元素的扩散。     

采用改进型钝化层的红外光电二极管及传感器列阵

美国专利US7544532 (2009年6月9日授权)本发明提供采用改进型钝化层的InSb红外光电二极管及传感器列阵,同时还提供了其制作方法。该方法的具体步骤如下:在n型衬底中形成光电二极管探测器区之前,用分子束外延技术在n型InSb衬底上沉积一层AlInSb钝化层;直接通过该AlInSb钝化层注入一种合适的P~+掺杂剂,以形成光电二极管探测器区;有选择地去除AlInSb钝化层,使InSb衬底的第一区暴露出来,然后在InSb衬底第一区形成栅接点;在光电二极管     

锑化铟离子注入退火技术研究

对锑化铟（InSb）铍离子（Be+）注入后的快速退火技术进行了研究,并对不同退火温度和时间的晶片进行了工艺实验,通过测试其PN结I-V特性,对比了不同快速退火条件对PN结特性的影响,确定在一定快速热退火条件下可以获得高质量的PN结,并对试验结果进行了分析。     

清洗工艺在太阳能电池工业化生产中的应用

太阳能电池工业化生产中采用前清洗工艺,可以有效地去除硅片表面的机械损伤层,清除表面油污和金属杂质,形成起伏不平的绒面进而增加对太阳光的吸收,增加PN结面积,最终提高硅晶体太阳电池的光电转换效率。后清洗工艺可以有效地进行湿法刻蚀和去除在扩散过程中形成的PSG。     

Characteristics of diffused P-N junctions in epitaxial layers

A one-dimensional analysis has been made to determine properties of diffused p-n junctions in epitaxial layers with nonuniform impurity concentration. Impurity diffusion from the surface and from the substrate is assumed to have complementary error function distribution. The transcendental equations obtained by analytical integration of Poisson's equation were evaluated numerically with the IBM 7090/94. Junction depth, impurity gradient and impurity level at the junction are given for a variety of diffusion parameters and impurity concentrations. In addition, graphs are presented, showing the relationship between reverse voltage and depletion layer thickness, capacitance per unit area, and peak electric field for the case of silicon. A comparison between the actual impurity profile and the usual linear approximation using the impurity gradient at the junction gives the range of depletion layer thickness or reverse voltage in which such an approximation is justified. Further, examples are presented of the electric field distribution in the depletion layer for several impurity concentration profiles. Calculated and experimentally determined values of some readily accessible junction characteristics show reasonably good agreement.     

基于热扩散制备平面PN结InSb红外焦平面芯片

研究了一种基于在锑化铟衬底材料上以热扩散工艺制备平面PN结的红外焦平面阵列(IRFPA)探测器芯片结构及其工艺流程。根据锑化铟材料的特性设计了新的焦平面器件制备流程,选择了等离子增强化学气相淀积(PECVD)淀积的非晶氧化硅(SiO2)、氮氧化硅(SiON)薄膜作为扩散工艺中的掩膜材料。在此基础上制备出了具有较好的I-V特性曲线的焦平面芯片。     

快速热退火对锑化铟表层化学配比的影响

锑化铟是一种窄禁带化合物半导体。近几年,它作为3～5μm红外探测器阵列的一种材料受到广泛的重视。为了制备高质量的锑化铟PN结光电二极管,铍注入与快速热退火(RTA)技术相结合是一种最佳的选择。本文借助俄歇电子能谱(AES)对在快速退火条件下锑化铟表层化学配比的偏离进行了系统的研究。     

Edge current induced failure of semiconductor PN junction during operation in the breakdown region of electrical characteristic

Typical blocking I-V characteristics are shown and analyzed for PN junctions exhibiting a breakdown region above 1000 V from commercial diodes and power MOSFETs. The leakage reverse current of PN junctions from commercial silicon devices available at this time has a flowing component at the semiconductor-passivant material interface around the junction edge.Part of the plotted experimental current-voltage characteristic fits to linear variation and deviation from this variation at higher applied voltage is attributed to non-controlled current flow in the interfacial layer, between the silicon and passivating material from the junction periphery. The thin interfacial layer including atomic layers both from the semiconductor and passivating dielectric material with fixed charges has imperfections resulted from the junction passivation process. For controlled-avalanche PN junctions no deviation from linear voltage dependence of the reverse current is possible until breakdown region practically at right knee appears. For other PN junctions deviation of the reverse current from linear variation results in a breakdown region with round knee and still with visible voltage dependence at current increase. Such soft breakdown region caused by the phenomena in the interfacial layer is exhibited at lower applied reverse voltage than the expected one for breakdown caused by charge carrier avalanche multiplication at the junction. Operation even for short in the soft breakdown region can lead to PN junction failure and for this reason, a maximum working permissible reverse voltage is specified in device data sheet with a value under the breakdown region. Junction failure consists in significantly lower reverse voltage than the initial one or even electrical short-circuit caused by a spot of material degradation in the interfacial layer from the junction periphery. Operation of the controlled-avalanche diode in the breakdown region is possible only for single pulse of short duration and at junction temperature not higher than 175 °C. Above 150-175 °C even for controlled-avalanche diodes deviation from linear variation of the reverse current has been observed and soft breakdown region can appear before the expected avalanche breakdown. Device failure after operation in the breakdown region, caused by spot of material degradation at the junction periphery has occurred in such conditions. For high voltage commercial power MOSFETs operation in the avalanche breakdown region is limited to 150 °C.     

InSb阳极氧化膜界面特性研究

用阳极氧化的方法在InSb衬底上生长氧化膜,并在阳极氧化膜上镀Cr/Au电极以制备MOS器件,通过分析77 K时MOS器件C-V特性,得出InSb-阳极氧化膜界面的掺杂浓度、界面态密度,氧化层中的固定电荷密度可动电荷密度等重要参数,分析其界面特性和制备工艺的关系,为InSb表面的钝化工艺提供参考。     

采用双面玻璃钝化工艺制造的双向可控硅

介绍一种特别的双向可控硅芯片的结构,该结构在芯片正面和背面均采用台面玻璃钝化工艺保护PN结终端以获得可靠的正反向阻断特性。描述了芯片的内部结构和制造工艺流程,并对封装过程中存在的主要问题和解决办法进行了分析和讨论。