磁控溅射ZnO基TFT的研究

采用直流磁控溅射在SiO2/n-Si(111)衬底上沉积了Al薄膜,经过光刻、刻蚀形成源漏极,再采用射频磁控溅射沉积ZnO薄膜作为有源层,成功制备了底栅顶接触结构的ZnO-TFT,Al膜厚135nm,ZnO膜厚110nm.实验结果表明,薄膜晶体管展示出明显的栅控特性以及饱和特性,ZnO薄膜沿C轴择优取向生长,且在可见光...     

底栅和顶栅结构全透明氧化锌薄膜晶体管的制备

报道了制备在50mm石英玻璃衬底上的透明氧化锌薄膜晶体管(ZnO-TFT),采用了底栅和顶栅两种结构进行比较.ZnO沟道层由射频磁控溅射方法制备,SiO2薄膜作为栅绝缘层.结果发现底栅结构的ZnO-TFT具有较好的电学性质,该器件工作在n沟道增强模式,具有较好的夹断效应和饱和特性,其场效应迁移率、阈值电压和电流开关比分别为18.4cm2/(V·s),-0.5V和104.顶栅结构的ZnO-TFT则工作在n沟道耗尽模式,没有明显的饱和特征.不同结构ZnO-TFT电学性质的差别可能是由于不同的ZnO/SiO2界面特性所致.两种结构的ZnO-TFT在可见光波段都有很高的光学透过率.     

底栅和顶栅结构全透明氧化锌薄膜晶体管的制备

报道了制备在50mm石英玻璃衬底上的透明氧化锌薄膜晶体管(ZnO-TFT),采用了底栅和顶栅两种结构进行比较.ZnO沟道层由射频磁控溅射方法制备,SiO2薄膜作为栅绝缘层.结果发现底栅结构的ZnO-TFT具有较好的电学性质,该器件工作在n沟道增强模式,具有较好的夹断效应和饱和特性,其场效应迁移率、阈值电压和电流开关比分别为18.4cm2/(V·s),-0.5V和104.顶栅结构的ZnO-TFT则工作在n沟道耗尽模式,没有明显的饱和特征.不同结构ZnO-TFT电学性质的差别可能是由于不同的ZnO/SiO2界面特性所致.两种结构的ZnO-TFT在可见光波段都有很高的光学透过率.     

退火温度对ZnO薄膜晶体管电学性能的影响

采用光刻剥离法和射频磁控溅射技术在带有热氧化层的硅衬底上制备了以氧化锌(ZnO)为沟道层的薄膜晶体管(ZnO-TFT).研究了不同温度退火处理对ZnO-TFT电学性能的影响,发现随着ZnO薄膜退火温度的增加,ZnO-TFT的阈值电压减小,电子的场效应迁移率增大.用原子力显微镜(AFM)对ZnO薄膜的微区结构进行观察,发现ZnO薄膜的平均粒径随退火温度的增加而增大,表明ZnO-TFT电学性质和沟道层薄膜晶粒大小密切相关.     

氩氧分压比对ZnO薄膜的结构及电学性能的影响

采用射频磁控溅射法制备了氧化锌基薄膜晶体管(ZnO-TFTS),研究了氩氧分压比对ZnO薄膜生长以及ZnO-TFT电学特性的影响。结果表明:氩氧分压比为40/16和40/8时制得的ZnO-TFT样品,都存在氧过量现象,生长晶向都存在一定左偏移,有源层沟道都为n型,均工作在增强型模式下,饱和特性都较好,且都呈现出一个较大的负方向漏电流,但氩氧分压比为40/16时制备的ZnO薄膜结晶性更好,其所对应的ZnO-TFT具有更高的场效应迁移率和开关电流比,以及更低的亚阈值摆幅。     

氩氧分压比对ZnO薄膜的结构及电学性能的影响

采用射频磁控溅射法制备了氧化锌基薄膜晶体管(ZnO-TFTS),研究了氩氧分压比对ZnO薄膜生长以及ZnO-TFT电学特性的影响。结果表明:氩氧分压比为40/16和40/8时制得的ZnO-TFT样品,都存在氧过量现象,生长晶向都存在一定左偏移,有源层沟道都为n型,均工作在增强型模式下,饱和特性都较好,且都呈现出一个较大的负方向漏电流,但氩氧分压比为40/16时制备的ZnO薄膜结晶性更好,其所对应的ZnO-TFT具有更高的场效应迁移率和开关电流比,以及更低的亚阈值摆幅。     

L-MBE法制备以ZnO为沟道层的薄膜晶体管

采用激光分子束外延法(L-MBE)在SiNx/Si(111)衬底上制备了高质量的ZnO薄膜,用X射线衍射(XRD)和原子力显微镜(AFM)对薄膜的晶体结构、表面形貌进行了表征,结果表明ZnO薄膜有高度的c轴择优取向,薄膜表面平整致密.并以ZnO薄膜为沟道层制作了薄膜晶体管(ZnO-TFT),该晶体管工作在n沟道增强模式,阈值电压为17.5V,电子的场迁移率达到1.05cm2/(V·s).     

L-MBE法制备以ZnO为沟道层的薄膜晶体管

采用激光分子束外延法(L-MBE)在SiNx/Si(111)衬底上制备了高质量的ZnO薄膜,用X射线衍射(XRD)和原子力显微镜(AFM)对薄膜的晶体结构、表面形貌进行了表征,结果表明ZnO薄膜有高度的c轴择优取向,薄膜表面平整致密.并以ZnO薄膜为沟道层制作了薄膜晶体管(ZnO-TFT),该晶体管工作在n沟道增强模式,阈值电压为17.5V,电子的场迁移率达到1.05cm2/(V·s).     

磁控溅射法制备高性能ZnO薄膜晶体管

研究了磁控溅射法制备的ZnO薄膜晶体管(TFT)。以NH3处理的热生长SiO2作为绝缘层,控制好Ar-O2比等条件溅射合适厚度的ZnO作为器件的有源层。实验表明,与普通条件下热生长的SiO2绝缘层硅片相比,NH3处理的高性能SiO2绝缘层Si片器件的载流子迁移率至少要高1个数量级以上;溅射条件在Ar-O2比25∶1情况下制作的器件性能最好;ZnO薄膜厚度也对ZnO-TFT性能有很大的影响。实验中,采用了4种膜厚,测试表明,其中25nm厚的ZnO薄膜迁移率最大。     

基片温度对基于Bi1.5Zn1.0Nb1.5O7栅绝缘层的ZnO基TFT性能的影响

在不同基片温度(RT、300、400、500和600℃)下,采用射频磁控溅射法制备了ZnO薄膜和BZN薄膜.研究表明,所制备的BZN薄膜拥有非晶态结构,ZnO薄膜具有c轴择优取向,在基片温度为500℃时,获得低的漏电流(10-7 A/cm2),比RT时的漏电流(10-4 A/cm2)低三个数量级.将所制备的ZnO薄膜和BZN薄膜分别作为ZnO-TFT的有源层和栅绝缘层,研究表明,在基片温度为500℃时,提高了器件性能,所取得的亚阈值摆幅(470 mV/dec.)是RT时的亚阈值摆幅(1 271 mV/dec.)的三分之一;界面态密度(3.21×1012 cm-2)是RT时的界面态密度(1.48×1013 cm-2)的五分之一.     

Active Layer Thickness Effects on the On-State Current and Pulse Measurement at Room Temperature on Deposited Zinc Oxide Thin-Film Transistors

This study reports on the fabrication of thin-film transistors (TFTs) with transparent zinc oxide (ZnO) semiconductors serving as the active channel and silicon dioxide (SiO₂) serving as the gate insulator. The ZnO films were deposited by radiofrequency magnetron sputtering at room temperature. Moreover, the effects of channel thickness on the structural and pulse current?Cvoltage characteristics of ZnO TFTs using a bottom gate configuration were investigated. As the channel thickness increased, the crystalline quality and the channel conductance were enhanced. The electrical characteristics of TFTs exhibited field-effect mobilities of 8.36?cm²/Vs to 16.40?cm²/Vs and on-to-off current ratios of 10⁸ to 10⁷ for ZnO layer thickness of 45?nm and 70?nm, respectively. The threshold voltage was in the range of 10?V to 31?V for ZnO layer thicknesses from 35?nm to 70?nm, respectively. The low deposition and processing temperatures make these TFTs suitable for fabrication on flexible substrates.     

A new alcohol-soluble electron-transporting molecule for efficient inverted polymer solar cells

A new electron-transporting material 4,7-diphenyl-1,10-phenanthroline-2,9-dicarboxylic acid (DPPA) was synthesized by modifying a n-type small molecule bathocuproine (BCP). The introduced carboxyl groups make DPPA soluble in polar solvent and compatible with large-scale solution-processing techniques. The anchoring of carboxyl on ZnO (or ITO) substrates helps to form a DPPA electron transporting layer, building an improved interfacial contact between the substrate and active layer. Furthermore, the highest occupied molecular orbital level of DPPA shifts to ?6.45 eV, which is 0.38 eV deeper than that of BCP, suggesting enhanced hole-blocking. Inverted polymer solar cells using P3HT:PCBM blend as the active layer and DPPA modified ZnO as the electron transporting layer were fabricated. A power conversion efficiency (PCE) of 3.55% was obtained, which is about 10% higher than that of the conventional ZnO buffered devices (3.25%). The DPPA was also used to replace ZnO as the sole electron-extracting layer, resulting in an improved PCE of 3.46%, which indicates that DPPA-ETL/ITO forms a better cathode than conventional ZnO/ITO.     

掺氮ZnO薄膜的光电特性及其薄膜晶体管研究

Using NH3 as nitrogen source gas, N-doped ZnO （ZnO：N） thin films in c-axis orientation were deposited on glass substrates by radio frequency magnetron sputtering at room temperature. The ZnO：N thin films display significant increase of resistivity and decrease of photoluminescence intensity. As-grown ZnO：N material was used as active channel layer and Si3N4 was used as gate insulator to fabricate thin-film transistor. The fabricated devices on glasses demonstrate typical field effect transistor characteristics.     

Optical and electrical properties of N-doped ZnO and fabrication of thin-film transistors

Using NH3 as nitrogen source gas, N-doped ZnO (ZnO:N) thin films in c-axis orientation were deposited on glass substrates by radio frequency magnetron sputtering at room temperature. The ZnO:N thin films display significant increase of resistivity and decrease of photoluminescence intensity. As-grown ZnO:N material was used as active channel layer and Si3N4 was used as gate insulator to fabricate thin-film transistor. The fabricated devices on glasses demonstrate typical field effect transistor characteristics.     

Holography and plasma oxidation for uniform nanoscale two dimensional channel formation of vertical organic field-effect transistors with suppressed gate leakage current

Vertical organic field-effect transistors (VOFETs) with nanoscale channel openings have been fabricated using pentacene as an active layer material. To achieve uniform nanoscale two-dimensional channel openings, a laser holography lithography has been introduced. Uniformly distributed and well-aligned holes with 250 nm diameter were successfully obtained with the laser holography lithography. VOFET devices with these channel openings have shown high on/off ratio of about 10³ without any further treatment. Gate leakage current was also decreased with an additional insulating layer generated on the gate electrode sidewall via plasma oxidation.     

Influence of substrate temperature on the performance of zinc oxide thin film transistor

Top-contact thin film transistors（TFTs） using radio frequency（RP） magnetron sputtering zinc oxide （ZnO） and silicon dioxide（SiO₂） films as the active channel layer and gate insulator layer,respectively,were fabricated.The performances of ZnO TFTs with different ZnO film deposition temperatures（room temperature, 100℃and 200℃） were investigated.Compared with the transistor with room-temperature deposited ZnO films, the mobility of the device fabricated at 200℃is improved by 94%and the threshold voltage shift is reduced from 18 to 3 V（after 1 h positive gate voltage stress）.Experimental results indicate that substrate temperature plays an important role in enhancing the field effect mobility,sharping the subthreshold swing and improving the bias stability of the devices.Atomic force microscopy was used to investigate the ZnO film properties.The reasons for the device performance improvement are discussed.     

Channel Protection Layer Effect on the Performance of Oxide TFTs

We have investigated the channel protection layer (PL) effect on the performance of an oxide thin film transistor (TFT) with a staggered top gate ZnO TFT and Al‐doped zinc tin oxide (AZTO) TFT. Deposition of an ultra‐thin PL on oxide semiconductor films enables TFTs to behave well by protecting the channel from a photo‐resist (PR) stripper which removes the depleted surface of the active layer and increases the carrier amount in the channel. In addition, adopting a PL prevents channel contamination from the organic PR and results in high mobility and small subthreshold swings. The PL process plays a critical role in the performance of oxide TFTs. When a plasma process is introduced on the surface of an active layer during the PL process, and as the plasma power is increased, the TFT characteristics degrade, resulting in lower mobility and higher threshold voltage. Therefore, it is very important to form an interface using a minimized plasma process.