深亚微米pMOS器件HCI退化建模与仿真方法

研究了深亚微米pMOS器件HCI(hot carrier injeotion)退化模型.采用流函数分析方法提出一种时变栅电流物理描述,基于这一栅电流模型改进了pMOS器件的HCI退化模型,并在该模型基础上提出一种HCI退化可靠性仿真方法,用于对静态应力条件下器件的HCI退化程度进行预测.最后给出了仿真结果对比.该方法已被用于XDRT可靠性工具中进行器件HCI退化分析.     

深亚微米HCI模型参数多目标全域提取方法

研究了一种建立在退化栅电流物理解析模型基础上的深亚微米pMOS器件HCI(hot carrier injection)退化模型.提出了一种基于L-M(Levenberg-Marquardt)算法的多目标响应全域优化提取策略,并对可靠性模型参数进行优化提取.分析了优化过程中由于参数灵敏度过低产生的问题并提出采用递归算法求解不同时刻栅电流注入电荷量的加速计算方法.最后,给出了最优化参数提取的结果,并且将测量值与理论值进行了比较,得到很好的一致性.     

深亚微米HCI模型参数多目标全域提取方法

研究了一种建立在退化栅电流物理解析模型基础上的深亚微米pMOS器件HCI(hot carrier injection)退化模型. 提出了一种基于L-M (Levenberg-Marquardt）算法的多目标响应全域优化提取策略，并对可靠性模型参数进行优化提取. 分析了优化过程中由于参数灵敏度过低产生的问题并提出采用递归算法求解不同时刻栅电流注入电荷量的加速计算方法. 最后，给出了最优化参数提取的结果，并且将测量值与理论值进行了比较,得到很好的一致性.     

低压5V pMOS器件在不同栅偏置应力下的热载流子注入退化机理研究

研究了低压pMOS器件热载流子注入HCI（hot-carrier injection）退化机理,分析了不同的栅压应力下漏极饱和电流（Idsat）退化出现不同退化趋势的原因。结合实测数据并以实际样品为模型进行了器件仿真,研究表明,快界面态会影响pMOS器件迁移率,导致Idsat的降低;而电子注入会降低pMOS器件阈值电压（Vth）,导致Idsat的上升。当栅压为-7.5V时,界面态的产生是导致退化的主要因素,在栅压为-2.4V的应力条件下,电子注入在热载流子退化中占主导作用。     

一个新的pMOSFET栅电流退化模型

研究了最大栅电流应力(即pMOSFET最坏退化情况)下pMOSFET栅电流的退化特性.实验发现,在最大栅电流应力下,pMOSFET栅电流随应力时间会发生很大下降,而且在应力初期和应力末期栅电流的下降规律均会偏离公认的指数规律.给出了所有这些现象的详细物理解释,并在此基础上提出了一种新的用于pMOSFET寿命评估的栅电流退化模型.     

一个新的pMOSFET栅电流退化模型

研究了最大栅电流应力 (即 p MOSFET最坏退化情况 )下 p MOSFET栅电流的退化特性 .实验发现 ,在最大栅电流应力下 ,p MOSFET栅电流随应力时间会发生很大下降 ,而且在应力初期和应力末期栅电流的下降规律均会偏离公认的指数规律 .给出了所有这些现象的详细物理解释 ,并在此基础上提出了一种新的用于 p MOSFET寿命评估的栅电流退化模型     

pMOS器件的热载流子注入和负偏压温度耦合效应

研究了在热载流子注入HCI(hot-carrier injection)和负偏温NBT(negative bias temperature)两种偏置条件下pMOS器件的可靠性.测量了pMOS器件应力前后的电流电压特性和典型的器件参数漂移,并与单独HCI和NBT应力下的特性进行了对比.在这两种应力偏置条件下,pMOS器件退化特性的测量结果显示高温NBT应力使得热载流子退化效应增强.由于栅氧化层中的固定正电荷引起正反馈的热载流子退化增强了漏端电场,使得器件特性严重退化.给出了NBT效应不断增强的HCI耦合效应的详细解释.     

pMOS器件的热载流子注入和负偏压温度耦合效应

研究了在热载流子注入HCI(hotcarrier injection)和负偏温NBT(negative bias temperature)两种偏置条件下pMOS器件的可靠性．测量了pMOS器件应力前后的电流电压特性和典型的器件参数漂移，并与单独HCI和NBT应力下的特性进行了对比．在这两种应力偏置条件下，pMOS器件退化特性的测量结果显示高温NBT应力使得热载流子退化效应增强．由于栅氧化层中的固定正电荷引起正反馈的热载流子退化增强了漏端电场，使得器件特性严重退化．给出了NBT效应不断增强的HCI耦合效应的详细解释．     

基于氧化铪的高k栅介质纳米MOSFET栅电流模型

运用一种全量子模型研究基于氧化铪的高k栅介质纳米MOSFET栅电流,该方法特别适用于高k栅介质纳米MOS器件,还能用于多层高k栅介质纳米MOS器件。使用该方法研究了基于氧化铪高k介质氮含量等元素对栅极电流的影响。结果显示,为最大限度减少MOS器件的栅电流,需要优化介质中氮含量、铝含量。     

高温正向栅电流下Ti/Pt/Au栅SiC MESFET的栅退化机理

SiC MESFET器件的性能强烈依赖于栅肖特基结的特性,而栅肖特基接触的稳定性直接影响其可靠性.针对SiC MESFET器件在微波频率的应用中射频过驱动导致高栅电流密度的现象,设计了两种栅极大电流的条件,观察栅肖特基接触和器件特性的变化,并通过对试验数据的分析,确定了栅的寄生并联电阻的缓慢退化是导致栅肖特基结和器件特性退化,甚至器件烧毁失效的主要原因.     

Effect of Floating-Body and Stress Bias on NBTI and HCI on 65-nm SOI pMOSFETs

Grounded-body (GB) core-logic/high-speed (HS) and input/output (I/O) silicon-on-insulator pMOSFETs from 65-nm technology are shown to degrade more than floating-body (FB) devices under negative bias temperature instability (NBTI) stress. However, in both cases, worst case degradation occurs when stressed under equal gate and drain voltages (V_g = V_d), whereby degradation is simultaneously induced by both NBTI and hot carrier injection (HCI) simultaneously ("concurrent HCI-NBTI"), the relative importance of each mechanism depending on the type of device and the bias level. The degradation of I/O pMOSFETs stressed under V_g = V_d at room temperature shows predominantly NBTI-like behavior at higher stress voltages, whereas it shows concurrent HCI-NBTI behavior at lower stress voltages. By contrast, the degradation of HS pMOSFETs stressed under V_g = V_d shows concurrent HCI-NBTI behavior over the entire stress bias range. In both cases, FB devices degrade more than GB devices for higher stress voltage values, but the FB effects weaken and the degradations become comparable for lower stress bias.     

一种新的SPICE BSIM3v3 HCI可靠性模型的建立及参数优化

研究中提出了用于描述HCI(热载流子注入)效应的MOSFET可靠性模型及其建模方法,在原BSIM3模型源代码中针对7个主要参数,增加了其时间调制因子,优化并拟合其与HCI加压时间(Stress time)的关系式,以宽长比为10μm/0.5μm5 V的MOSFET为研究对象,在开放的SPICE和BSIM3源代码对模型库文件进行修改,实现了该可靠性模型。实验表明,该模型的测量曲线与参数提取后的I-V仿真曲线十分吻合,因而适用于预测标准工艺MOS器件在一定工作电压及时间下性能参数的变化,进而评估标准工艺器件的寿命。     

An efficient temperature dependent hot carrier injection reliability simulation flow

This paper presents an efficient temperature dependent hot carrier injection reliability simulation flow which is scalable. The flow makes use of some efficient techniques at different design hierarchical levels to enable full chip simulation with a fast run time and high enough accuracy. While the transistor-level HCI effect is modeled based on the conventional reaction–diffusion (R–D) framework, the gate-level characterization method combines HSpice simulation and piecewise linear curve fitting to model the impact of HCI effect over the time. Also, as one of the ways to improve the speed of the simulation, only the NMOS transistors, which suffer much more from the HCI effect, are considered in the modeling. In addition, among these devices, only those which are more significantly affected are included. For each cell, only the transitions which induce the HCI impact are included. Finally, to improve the efficiency of the circuit simulation, logic cells in the circuit are classified into two groups of critical and non-critical where the critical (non-critical) ones are simulated using fine (coarse) granularity simulation time steps. The proposed method reduces the simulation time without losing much of accuracy. Also, due to the considerable impact of the temperature on the reliability, at all levels of the proposed simulation flow, the impact of the temperature on the impact of the HCI phenomena is modeled. The simulations performed on some benchmarks reveal that the proposed circuit-level HCI modeling is able to reduce the runtime of calculating the threshold voltage and mobility drifts of the gates significantly without sacrificing accuracy unacceptably. Also, the circuit-level simulations indicate an about 19% increase in the average of the HCI-induced delay degradation of the benchmarks when the temperature rises from 20 °C to 100 °C.     

An accurate MOSFET aging model for 28 nm integrated circuit simulation

MOSFET device aging represents a significant challenge for the IC industry, being increasingly more responsible for reliability failure in advanced process technology nodes. As the device electrical characteristics, such as threshold voltage and drain current, degrade with time, circuit performance also deteriorates, resulting in shorter lifetime and narrower safety margins between requirements and actual product reliability.Major device aging mechanisms include the hot-carrier injection (HCI), the negative bias-temperature instability (NBTI) for p-channel MOSFETs, and the positive bias-temperature instability (PBTI) for n-channel devices.HCI in NMOS and PMOS has been known for many years. In the presence of high electric fields, carriers are injected from the drain end of the channel into the gate dielectric, changing its electrical properties over time.PMOS NBTI has been studied in the past, and it continues to present a challenge for today’s technologies. NMOS PBTI is a phenomenon notably present in high-k metal-gate stacks. The partial recovery of degradation, an effect important for both phenomena, has been particularly challenging to model for circuit simulation, and not addressing it may result in overly pessimistic circuit lifetime predictions.In this paper we present an accurate, physics-based MOSFET aging model that encompasses degradation due to HCI, NBTI and PBTI. The model formulation on bias, geometry and temperature, and a unique methodology for modeling the AC partial-recovery effect of BTI are detailed and analyzed. The extraction methodology of the aging model parameters is further described. The model is implemented in an efficient MOSRA flow for SPICE and Fast SPICE circuit simulation, which has been successfully used to improve IC reliability-related yield in numerous 28 nm tapeouts.     

pMOS器件NBTI界面电荷引起耦合的数值模拟分析

从二维模拟pMOS器件得到沟道空穴浓度和栅氧化层电场,用于计算负栅压偏置温度不稳定性NBTI(Negative bias temperature instability)效应的界面电荷的产生,是分析研究NBTI可靠性问题的一种有效方法。首先对器件栅氧化层/硅界面的耦合作用进行模拟,通过大量的计算和已有的实验比对分析得出:当NBTI效应界面电荷产生时,栅氧化层电场是增加了,但并没有使界面电荷继续增多,是沟道空穴浓度的降低决定了界面电荷有所减少(界面耦合作用);当界面电荷的产生超过1012/cm2时,界面的这种耦合作用非常明显,可以被实验测出;界面耦合作用使NBTI退化减小,是一种新的退化饱和机制,类似于"硬饱和",但是不会出现强烈的时间幂指数变化。     

Degradation characteristics of STI and MESA-isolated thin-film SOICMOS

I-V degradations of STI (shallow trench isolation) and MESA-isolated SOI are reported for devices with a given threshold voltage design (V_TH≈0.4 V). We show that degradation characteristics of the STI and MESA SOI are quite different from strain-induced degradation observed in LOCOS SOI. It is found that the nMOSFET's I-V degradation becomes more pronounced while pMOSFETs remain relatively constant as the silicon thickness (t_si) is reduced. The reduction of nMOSFET's drive current is attributed to the mobility degradation as the channel concentration is increased, whereas for the pMOSFETs, due to the lesser sensitivity of the hole to the Coulomb scattering, no degradation is observed     

边缘注入对H型栅SOI pMOSFETs亚阈值泄漏电流的影响

就不同边缘注入剂量对H型栅SOI pMOSFETs亚阈值泄漏电流的影响进行了研究。实验结果表明不足的边缘注入将会产生边缘背栅寄生晶体管，并且在高的背栅压下会产生明显的泄漏电流。分析表明尽管H型栅结构的器件在源和漏之间没有直接的边缘泄漏通路，但是在有源扩展区部分，由于LOCOS技术引起的硅膜减薄和剂量损失仍就促使了边缘背栅阈值电压的降低。     

Influence of fin number on hot-carrier injection stress induced degradation in bulk FinFETs

In this paper, hot-carrier injection (HCI) stress has been used to investigate the reliability of n-channel FinFET devices with different fin numbers. Threshold voltage (V_TH) shift, subthreshold swing and transconductance variation were extracted to evaluate the degradation of the device under stress. FinFET devices with fewer fins show more serious performance degradation due to hot-carrier injection stress. It is suggested that the existing of coupling effect between neighboring fins reduces the inversion charge density and equivalent electric field in multi-fin devices, which causes better reliability than single-fin devices.     

A Model With Temperature-Dependent Exponent for Hot-Carrier Injection in High-Voltage nMOSFETs Involving Hot-Hole Injection and Dispersion

An improved hot-hole-involved interface-state generation model is proposed for hot-carrier injection (HCI) degradation in high-voltage (HV) nMOSFETs. This model is based on experiments over a wide range of temperatures, voltage conditions, simulation results, and the underlying physical mechanisms. The model provides a thorough picture of an HCI system in HV nMOSFETs, with hot-hole injection related to an additional maximum electric-field region. The hot-hole injection in HCI is assumed to introduce deeper localized hydrogen states in gate-oxide films than that in negative-bias temperature instabilities. This result facilitates the dispersive transport of hydrogen. Therefore, HCI degradation in HV transistors is explained within the framework of disorder-controlled hydrogen kinetics. The power-law model can successfully predict temperature dependences for HCI degradation.