Design to suppress return-back leakage current of charge pump circuit in low-voltage CMOS process

A new charge pump circuit has been proposed to suppress the return-back leakage current without suffering the gate-oxide reliability problem in low-voltage CMOS process. The four-phase clocks were used to control the charge-transfer devices turning on and turning off alternately to suppress the return-back leakage current. A test chip has been implemented in a 65-nm CMOS process to verify the proposed charge pump circuit with four pumping stages. The measured output voltage is around 8.8 V with 1.8-V supply voltage to drive a capacitive output load, which is better than the conventional charge pump circuit with the same pumping stages. By reducing the return-back leakage current and without suffering gate-oxide overstress problem, the new proposed charge pump circuit is suitable for applications in low-voltage CMOS IC products.     

Ultra-High-Voltage Charge Pump Circuit in Low-Voltage Bulk CMOS Processes With Polysilicon Diodes

An on-chip ultra-high-voltage charge pump circuit realized with the polysilicon diodes in the low-voltage bulk CMOS process is proposed in this work. Because the polysilicon diodes are fully isolated from the silicon substrate, the output voltage of the charge pump circuit is not limited by the junction breakdown voltage of MOSFETs. The polysilicon diodes can be implemented in the standard CMOS processes without extra process steps. The proposed ultra-high-voltage charge pump circuit has been fabricated in a 0.25-mum 2.5-V standard CMOS process. The output voltage of the four-stage charge pump circuit with 2.5-V power-supply voltage (VDD=2.5 V) can be pumped up to 28.08 V, which is much higher than the n-well/p-substrate breakdown voltage (~18.9 V) in a 0.25-mum 2.5-V bulk CMOS process     

A high efficiency charge pump circuit for low power applications

A high efficiency charge pump circuit is designed and realized. The charge transfer switch is biased by the additional capacitor and transistor to eliminate the influence of the threshold voltage. Moreover, the bulk of the switch transistor is dynamically biased so that the threshold voltage gets lower when it is turned on during charge transfer and gets higher when it is turned off. As a result, the efficiency of the charge pump circuit can be improved. A test chip has been implemented in a 0.18 μm 3.3 V standard CMOS process. The measured output voltage of the eight-pumping-stage charge pump is 9.8 V with each pumping capacitor of 0.5 pF at an output current of 0.18 μA, when the clock frequency is 780 kHz and the supply voltage is 2 V. The charge pump and the clock driver consume a total current of 2.9 μA from the power supply. This circuit is suitable for low power applications.     

PMOS-switching dual-path charge pump in standard twin-well CMOS technology

In this article a new charge pump circuit is presented, which is feasible for implementation with the standard twin-well CMOS process. The proposed charge pump employs PMOS-switching dual charge-transfer paths and a simple two-phase clock. Since charge transfer switches are fully turned ON during each half of the clock cycle, they transfer charges completely from the present stage to the next stage without suffering threshold voltage drop. During one clock cycle, the pump transfers charges twice through two pumping paths which are operating alternately. Test chips have been fabricated in a 0.35-μm twin-well CMOS process. The output voltage of a 4-stage charge pump with each pumping capacitor of 7.36 pF measures 6.7 V under a 1.5 V power supply and 20 MHz clock frequency. It can supply a maximum load current of about 180 μA. Although the proposed circuit exhibits somewhat inferior performances against triple-well charge pumps using additional mask and process steps, it shows at least 60% higher voltage gain at V _DD = 0.9 V, approximately 10% higher peak power efficiency at V _DD = 1.5 V, much larger output current drivability and faster initial output rising than traditional twin-well charge pumps. This new pumping efficient circuit is suitable for design applications with a low-cost standard twin-well CMOS process.     

A regulated charge pump with small ripple voltage and fast start-up

A regulated charge pump circuit is realized in a 3.3-V 0.13-/spl mu/m CMOS technology. The charge pump exploits an automatic pumping control scheme to provide small ripple output voltage and fast start-up by decoupling output ripple and start-up time. The automatic pumping control scheme is composed of two schemes, an automatic pumping current control scheme and an automatic pumping frequency control scheme. The former automatically adjusts the size of pumping driver to reduce ripple voltage according to output voltage. The latter changes the pumping period by controlling a voltage-controlled oscillator (VCO). The output frequency of the VCO varies from 400 kHz to 600 kHz by controlling the input bias voltage of the VCO. The prototype chip delivers regulated 4.5-V output voltage from a supply voltage of 3.3 V with a flying capacitor of 330 nF, while providing 30 mA of load current. The area is 0.25 mm/sup 2/ and the measured output ripple voltage is less than 33.8 mV with a 2-/spl mu/F load capacitor. The power efficiency is greater than 70% at the range of load current from 1 to 30 mA. An analytical model for ripple voltage and recovery time is proposed demonstrating a reasonable agreement with SPICE simulation results.     

A 150-nA 13.4-ppm/℃switched-capacitor CMOS sub-bandgap voltage reference

A nanopower switched-capacitor CMOS sub-bandgap voltage reference has been implemented using a Chartered 035-μm 3.3-V/5-V dual gate mixed-signal CMOS process.The proposed circuit generates a precise sub-bandgap voltage of 1 V.The temperature coefficient of the output voltage is 13.4 ppm/℃with the temperature varying from -20 to 80℃.The proposed circuit operates properly with the supply voltage down to 1.3 V,and consumes 150 nA at room temperature.The line regulation is 0.27%/V.The power supply rejection ratio at 100 Hz and 1 MHz is -39 dB and -51 dB,respectively.The chip area is 0.2 mm~2.     

Gain-Boosting Charge Pump for Current Matching in Phase-Locked Loop

The charge pump (CP) circuit is a key element in a phase-locked loop (PLL). Its function is to transform the Up and Down signals from the phase/frequency detector into current. In CMOS CPs, which have Up and Down switches made of p-channel MOS and n-channel MOS, respectively, a current mismatch occurs when dumping the charge to the loop filter. This current mismatch of the CP in the PLL generates fluctuations in the voltage-controlled-oscillator input and subsequently, a large phase noise on the PLL output signals. In this brief, a new CP with good current matching characteristics is proposed. By using a simple gain-boosting circuit, good current matching characteristics can be achieved with less than 0.1% difference of the Up/Down current over the CP output voltage ranges of 0.8-2.2 V and 0.5-1.2 V on 0.35-mum 3.3-V and 0.18-mum 1.8-V CMOS processes, respectively. The proposed CP circuit is simulated and verified by HSPICE with 0.35-mum 3.3-V and 0.18-mum 1.8-V CMOS parameters     

On-chip high voltage charge pump in standard low voltage CMOS process

An on-chip high voltage tolerant 4VDD charge pump with symmetrical architecture in a standard low voltage 1.8 V 0.18 /spl mu/m CMOS process is presented. For a 250 k/spl Omega/ load, circuit efficiency of the charge pump is approximately 71%. All the MOS transistors satisfy typical voltage stress related reliability requirements for standard low voltage CMOS devices.     

A technique to increase the efficiency of high-voltage charge pumps

A charge pump that utilizes a MOSFET body diode as a charge transfer switch is discussed. The body diode is characterized and a body diode model is developed for simulating the charge pump circuit. A 10% increase of voltage gain has been achieved in the proposed switching technique when compared with a traditional Dickson charge pump. The top plate and bottom plate switching technique have also been illustrated to improve the efficiency of the charge pump. A six-stage Dickson charge pump was designed to produce a 19 V output from a 3.3-V supply, using a 4 MHz, two-phase nonoverlapping clock signal driving the charge pump. The design was fabricated in a 0.35-/spl mu/m SOI CMOS process. An efficiency of 79% is achieved at a load current of approximately 19 /spl mu/A.     

一种应用于MEMS麦克风偏置电路的电荷泵设计

MEMS麦克风需要一个高于10 V的偏置电压才能工作,这个高电压一般由内部电荷泵电路产生.在传统Dickson电荷泵结构的基础上,提出一种改进的电荷泵结构.它首先将非重叠时钟的幅度加倍,然后用幅度加倍的时钟作为电荷泵的驱动时钟,取得了明显的升压效果.Hspice仿真结果表明,电源电压为1.4V时,6级二极管-电容升压单元就可以实现10.7674 V的输出电压.与传统的Dickson升压电路相比,改进型电荷泵的升压单元减少了4级,且其核心部分的面积减小了21％,功耗降低了40％(参考SMIC 0.35 μm CMOS工艺).     

Electrostatic discharge (ESD) protection for CMOS output buffers in scaled-down VLSI technology

To provide area-efficient output ESD protection for the scaled-down CMOS VLSI, a new output ESD protection is proposed. In the new output ESD protection circuit, there are two novel devices, the PTLSCR (PMOS-trigger lateral SCR) and the NTLSCR (NMOS-trigger lateral SCR). The PTLSCR is in parallel and merged with the output PMOS, and the NTLSCR is in parallel and merged with the output NMOS, to provide area-efficient ESD protection for CMOS output buffers. The trigger voltages of PTLSCR and NTLSCR are lowered below the breakdown voltages of the output PMOS and NMOS in the CMOS output buffer. The PTLSCR and NTLSCR are guaranteed to be turned on first before the output PMOS or NMOS are broken down by the ESD voltage. Experimental results have shown that the PTLSCR and NTLSCR can sustain over 4000 V (700 V) of the human-body-model (machine-model) ESD stresses within a very small layout area in a 0.6 μm CMOS technology with LDD and polycide processes. The noise margin of the proposed output ESD protection design is greater than 8 V (lower than −3.3 V) to avoid the undesired triggering on the NTLSCR (PTLSCR) due to the overshooting (undershooting) voltage pulse on the output pad when the IC is under normal operating conditions with 5 V VDD and 0 V VSS power supplies.     

一种适用于MEMS麦克风的新型恒压电荷泵设计

实现了一种新型恒压输出电荷泵电路,通过选择合理的电荷泵结构能有效抑制反向电流及衬底电流,并通过一种负反馈稳压电路得到低纹波且不随电源电压变化的稳压输出,非常适用于MEMS麦克风。该电路采用MIXIC0.35μm标准CMOS工艺实现,测试结果表明该电路能自适应2.8～3.6V的电源电压变化,输出稳定的9V直流电压。     

Design and Analysis of an Ultrahigh-Speed Glitch-Free Fully Differential Charge Pump With Minimum Output Current Variation and Accurate Matching

An ultrahigh-speed fully differential charge pump with minimum current mismatch and variation is proposed in this brief. A mismatch suppression circuit is employed to minimize the mismatch between the charging and discharging currents, which minimizes the steady-state phase error in a phase-locked loop (PLL). A variation suppression circuit is proposed to minimize output current variation with the change of output voltage, which reduces the variation of the bandwidth in a PLL. Techniques are proposed to suppress both low-speed glitches and high-speed glitches in the output current to allow glitch-free operation of the charge pump with ultrafast input pulses. The differential charge pump is designed and simulated under the power supply of 3.3 V in TSMC 0.35-$mu$m CMOS technology to verify the effectiveness of the proposed techniques.     

Design of a high performance CMOS charge pump for phase-locked loop synthesizers

A new high performance charge pump circuit is designed and realized in 0.18μm CMOS process. A wide input ranged rail-to-rail operational amplifier and self-biasing cascode current mirror are used to enable the charge pump current to be well matched in a wide output voltage range.Furthermore,a method of adding a precharging current source is proposed to increase the initial charge current,which will speed up the settling time of CPPLLs.Test results show that the current mismatching can be less than 0.4%in the output voltage range of 0.4 to 1.7 V,with a charge pump current of 100μA and a precharging current of 70μA.The average power consumption of the charge pump in the locked condition is around 0.9 mW under a 1.8 V supply voltage.     

New Curvature-Compensation Technique for CMOS Bandgap Reference With Sub-1-V Operation

A new sub-1-V curvature-compensated CMOS bandgap reference, which utilizes the temperature-dependent currents generated from the parasitic n-p-n and p-n-p bipolar junction transistor devices in the CMOS process, is presented. The new proposed sub-1-V curvature-compensated CMOS bandgap reference has been successfully verified in a standard 0.25-$muhboxm$CMOS process. The experimental results have confirmed that, with the minimum supply voltage of 0.9 V, the output reference voltage at 536 mV has a temperature coefficient of 19.5$hboxppm/^circhboxC$from 0$^circhboxC$to 100$~^circhboxC$. With a 0.9-V supply voltage, the measured power noise rejection ratio is$-hbox25.5~hboxdB$at 10 kHz.     

一种DC-DC升压型开关电源的低压启动方案

设计了一种DC-DC升压型开关电源的低压启动电路,该电路采用两个在不同电源电压范围内工作频率较稳定的振荡器电路,利用电压检测模块进行合理的切换,解决了低输入电压下电路无法正常工作的问题,并在0.5μm CMOS工艺库（VthN=0.72 V,VthP=-0.97 V）下仿真。仿真结果表明,在0.8 V低输入电压时,通过此升压型开关电源,可以将VDD升高至3.3 V。     

A sub-2.0 V BiCMOS logic circuit with a BiCMOS charge pump

A BiCMOS logic circuit with very small input capacitance has been developed, which operates at low supply voltages. A High-beta BiCMOS (Hβ-BiCMOS) gate circuit which fully utilizes the bipolar transistor features achieves 10 times the speed of a CMOS gate circuit with the same input capacitance and operating at 3.3 V supply voltage. In order to lower the minimum supply voltage of Hβ-BiCMOS, a BiCMOS circuit configuration using a charge pump to pull up the output high level of the BiCMOS gate circuit is proposed. By introducing a BiCMOS charge pump, Hβ-BiCMOS achieves very high speed operation at sub-2.0 V supply voltage. It has also been demonstrated that only a very small number of charge pump circuits are required to drive a large number of Hβ-BiCMOS gate circuits     

一种低压改进型MOS电荷泵电路的设计

针对使用标准CMOS技术实现的传统电荷泵输出电压较低的不足,文中提出将基本的电荷转移开关进行改进的MOS电荷泵,在泵送增益增加电路的基础上,通过在泵的输出级增加第3个控制信号来提高电荷泵的电压增益,以得到更高的输出电压,将其作为无线传感器的能量收集电路。仿真结果表明,该改进型电荷泵电路适合于低电压设备,并具有较高的泵送增益。其输出电压在同类电荷泵中最高,在1.5 V电源条件下,可高达8.5 V。     

A new inverter-based charge pump circuit with high conversion ratio and high power efficiency

The current paper presents a new inverter-based charge pump circuit with high conversion ratio and high power efficiency. The proposed charge pump, which consists of a PMOS pass transistor, inverter-based switching transistors, and capacitors, can improve output voltage and conversion ratio of the circuit. The proposed charge pump was fabricated with TSMC 0.35 μm 2P4M CMOS technology. The chip area without pads is only 0.87 mm×0.65 mm. The measured results show that the output voltage of the four-stage charge pump circuit with 1.8 V power supply voltage (V_DD=1.8 V) can be pumped up to 8.2 V. The proposed charge pump circuit achieves efficiency of 60% at 80 μA.     

低电源电压条件下的双阈值电压泵

由于存在逆向电流,利用电流传输开关特性的改进型的电压泵（NCP-1）的电压增益被大大减弱.本论文提供了一个新的方法.通过使用双阈值电压CMOS代替单阈值电压CMOS,不但消除了逆向电流,而且对低电压有很好的放大增益.PSPICE模拟结果,当电源电压为0.5V时,6级电压泵可使输出电压放大到2.68V.