A 2-V 23-/spl mu/A 5.3-ppm//spl deg/C curvature-compensated CMOS bandgap voltage reference

A high-order curvature-compensated CMOS bandgap reference, which utilizes a temperature-dependent resistor ratio generated by a high-resistive poly resistor and a diffusion resistor, is presented in this paper. Implemented in a standard 0.6-/spl mu/m CMOS technology with V/sub thn//spl ap/|V/sub thp/|/spl ap/0.9 V at 0/spl deg/C, the proposed voltage reference can operate down to a 2-V supply and consumes a maximum supply current of 23 /spl mu/A. A temperature coefficient of 5.3 ppm//spl deg/C at a 2-V supply and a line regulation of /spl plusmn/1.43 mV/V at 27/spl deg/C are achieved. Experimental results show that the temperature drift is reduced by approximately five times when compared with a conventional bandgap reference in the same technology.     

Design of sub-1-V CMOS bandgap reference circuit using only one BJT

This paper describes new CMOS bandgap reference (BGR) circuits capable of providing sub-1-V voltage reference while using only one BJT. The circuits use the concept of reverse bandgap voltage principle (RBVP) to generate attenuated versions of the silicon bandgap voltage of 1.205?V. Also, as opposed to the previously known sub-1-V BGR by Banba et?al. (IEEE J Solid State Circuits 34:670?C674, 1999), the circuits can be operated with lower supply voltage down to a 1.3?V supply. Based on the scheme, a 550?mV BGR is implemented in 65?nm CMOS process, with peak-to-peak variation of 7.19?mV across devices corners, temperature range of ?20 to 80° and supply range of 1.6?C2.0?V.     

A sub-1-V 15-ppm/°C CMOS bandgap voltage reference withoutrequiring low threshold voltage device

A sub-1-V CMOS bandgap voltage reference requiring no low threshold voltage device is introduced in this paper. In a CMOS technology with V_thn ≈ |V_thp| ≈ 0.9 V at 0°C, the minimum supply voltage of the proposed voltage reference is 0.98 V, and the maximum supply current is 18 μA. A temperature coefficient of 15 ppm/°C from 0°C to 100°C is recorded after trimming. The active area of the circuit is about 0.24 mm²     

一种新型的电流模式曲率补偿带隙基准源

提出了一种新型的低压带隙基准源,与传统的带隙基准不同,该电路引入了第三个电流,以消除双极型晶体管射基电压的温度非线性项,从而实现曲率补偿。采用0．18μmCMOS工艺进行设计验证,HSpice仿真结果表明,室温下的输出电压为623mV,-55～＋125℃范围内的温度系数为4．2ppm／℃,1．0～2．1V之间的电源调整率为0．9mV／V。     

Design and verification of a 10-bit 1.2-V 100-MSPS D/A IP core based on a 0.13-μm low power CMOS process

Based on a low supply voltage curvature-compensated bandgap reference and central symmetry Q~2 random walk NMOS current source layout routing method,a 1.2-V 10-bit 100-MSPS CMOS current-steering digital-to-analog converter is implemented in a SMIC 0.13-μm CMOS process.The total consumption is only 10 mW from a single 1.2-V power supply,and the integral and differential nonlinearity are measured to be less than 1 LSB and 0.5 LSB, respectively.When the output signal frequency is 1-5 MHz at 100-MSPS samplin...     

A novel precision curvature-compensated bandgap reference

A high precision high-order curvature-compensated bandgap reference compatible with the standard CMOS process, which uses a compensation proportional to V_TlnT realized by utilizing voltage to current converters and the voltage current characteristics of a base-emitter junction, is presented. Experiment results of the proposed bandgap reference implemented with the CSMC 0.5-μm CMOS process demonstrate that a temperature coefficient of 3.9 ppm/℃ is realized at 3.6 V power supply, a power supply rejection ratio of 72 dB is achieved, and the line regulation is better than 0.304 mV/V dissipating a maximum supply current of 42μA.     

Sub-1-V Supply Self-Adaptive CMOS Image Sensor Cell With 86-dB Dynamic Range

This letter presents a high dynamic range CMOS active pixel structure operating at a sub-1-V supply voltage, which is implemented using a standard 0.18-mum CMOS logic process. In order to improve the output voltage swing range and associated pixel dynamic range at a low supply voltage, a pMOS reset structure is incorporated into the pixel structure along with a photogate pixel structure based on the self-adaptive photosensing operation. At a low supply voltage of 0.9 V, the new pixel provides an output voltage swing range of 0.41 V and a high dynamic range of 86 dB, which is the highest among the reported pixel structures up to date operating at sub-1-V     

A 2.2-V 2.9-ppm/℃BiCMOS bandgap voltage reference with full temperature-range curvature-compensation

A high precision high-order curvature-compensated bandgap reference compatible with the standard Bi-CMOS process,which uses a simple structure to realize a novel exponential curvature compensation in lower temperature ranges,and a piecewise curvature correction in higher temperature ranges,is presented.Experiment results of the proposed bandgap reference implemented with a 0.6-μm BCD process demonstrate that a temperature coefficient of 2.9 ppm/℃is realized at a 3.6-V power supply,a power supply rejectio...     

A Sub-1-V Low-Noise Bandgap Voltage Reference

A new sub-1-V bandgap voltage reference is presented in this paper, which has advantages over the prior arts in terms of output noise and compatibility with several fabrication processes. The topology allows the reference to operate with a supply voltage as low as 1 V by employing the reverse bandgap voltage principle (RBVP). It also has an attractive low-noise output without the use of a large external filtering capacitor. The design was fabricated with a 0.5-mum BiCMOS process, but it is compatible with most CMOS and BiCMOS fabrication processes. The entire die area is approximately 0.4 mm², including all test pads and dummy devices. Theoretical analysis and experimental results show that the output noise spectral density is 40 nV/radicHz with a bias current of 20 muA. Moreover, the peak-to-peak output noise in the 0.1-10 Hz band is only 4 muV. The untrimmed reference has a mean output voltage of 190.9 mV at room temperature, and it has a temperature coefficient in the -40degC to +125degC range of 11 ppm/degC (mean) with a standard deviation of 5 ppm/degC.     

一种二阶曲率补偿带隙基准电压源

利用CMOS工艺中Poly电阻和N-well电阻温度系数的不同,设计了一种输出可调的二阶曲率补偿带隙基准电压源.采用Chartered 0.35μm CMOS工艺模型,使用Cadence工具对电路进行了仿真,结果表明电路在电源电压为1.8V时可正常工作,当其在1.8～3V范围内变化时,基准电压变化仅有3.8mV;工作电压为2V时,输出基准电压在-40°C到80°C的温度范围内温度系数为1.6ppm/°C,工作电流为24μA,低频下的电源抑制比为-47dB.该带隙基准电压源的设计可以满足低温漂、高稳定性、低电源电压以及低功耗的要求.     

Low-power bandgap references featuring DTMOSTs

This paper describes two CMOS bandgap reference circuits featuring dynamic-threshold MOS transistors. The first bandgap reference circuit aims at application in low-voltage, low-power ICs that tolerate medium accuracy. The circuit runs at supply voltages down to 0.85 V while consuming only 1 μW; the die area is 0.063 mm² in a standard digital 0.35-μm CMOS process. The second bandgap reference circuit aims at high accuracy operation (σ=0.3%) without trimming. It consumes approximately 5 μW from a 1.8-V supply voltage and occupies 0.06 mm² in a standard 0.35-μm CMOS process     

A 1.2-V 19.2-mW 10-bit 30-MS/s pipelined ADC in 0.13-icm CMOS

A 10-bit 30-MS/s pipelined analog-to-digital converter (ADC) is presented.For the sake of lower power and area,the pipelined stages are scaled in current and area,and op amps are shared between the successive stages.The ADC is realized in the 0.13-tt,m 1-poly 8-copper mixed signal CMOS process operating at 1.2-V supply voltage.Design approaches are discussed to overcome the challenges associated with this choice of process and supply voltage,such as limited dynamic range,poor analog characteristic devices,the limited linearity of analog switches and the embedded sub-1-V bandgap voltage reference.Measured results show that the ADC achieves 55.1-dB signal-to-noise and distortion ratio,67.5-dB spurious free dynamic range and 19.2-mW power under conditions of 30 MSPS and 10.7-MHz input signal.The FoM is 0.33 pJ/step.The peak integral and differential nonlinearities are 1.13 LSB and 0.77 LSB,respectively.The ADC core area is 0.94 mm2.     

A CMOS bandgap reference circuit with sub-1-V operation

This paper proposes a CMOS bandgap reference (BGR) circuit, which can successfully operate with sub-1-V supply, In the conventional BGR circuit, the output voltage V_ref is the sum of the built-in voltage of the diode V_f and the thermal voltage V_T of kT/q multiplied by a constant. Therefore, V_ref is about 1.25 V, which limits a low supply-voltage operation below 1 V. Conversely, in the proposed BGR circuit, V_ref has been converted from the sum of two currents; one is proportional to V_f and the other is proportional to V_T. An experimental BGR circuit, which is simply composed of a CMOS op-amp, diodes, and resistors, has been fabricated in a conventional 0.4-μm flash memory process. Measured V_ref is 518±15 mV (3σ) for 23 samples on the same wafer at 27-125°C     

±1.5V 1.37×10~(-6)/℃电流模式CMOS带隙基准源的分析与设计

设计了电流模式曲率补偿的CMOS带隙基准源,基本原理是利用两个偏置在不同电流特性下的三极管,得到关于温度的非线性电流,补偿VEB的高阶温度项。用标准的0.6μm CMOS BSIM3v3模型库对该带隙基准源进行了仿真,结果表明在±1.5 V的电源电压下,输出基准电压为-1.418 55 V,-55～125℃较宽的温度范围内,输出电压的变化只有0.35 mV,有效温度系数达到1.37×10-6/℃。同时,带隙基准源具有较高的电源抑制比,在2 kHz下达到73 dB。     

一种曲率补偿CMOS带隙基准源

介绍了一种可提供1.438 V基准电压的曲率补偿带隙基准源.采用一种极其简单有效的方法,直接实现曲率补偿.该电路采用双金属双多晶硅0.6 μm CMOS工艺制造,用于驱动一个10位20 MS/s A/D转换器.仿真结果显示,该带隙基准源在室温5 V电源电压下,仅耗用64 μA电流;0～80°C范围内,温度系数为13.7 ppm/K, 电源电压抑制比为64.7 dB.     

一种低压新型曲率补偿基准电压源设计

基于Chrt0.35 μmCMOS工艺,设计了一种基于亚阈值工作区的一阶温度补偿和I²_PTAT电路组成的带隙基准电压源。芯片测试结果表明,电路在1.2 V电源电压下便可工作;在温度-20~120 ℃范围内,基准电压源平均温度系数＜2×10^-6/℃。该带隙基准源具有良好的可应用于高精度模数转换器(ADC)、数模转换器(DAC)和系统集成芯片(SOC)中。     

A novel 0.84 ppm/°C CMOS curvature-compensated bandgap with 1.2 V supply voltage

This paper proposes a novel CMOS curvature-compensated bandgap reference (BGR) by using a new full compensation technique. The theory behind the proposed full compensation technique is analyzed. The proposed BGR is designed and implemented using 0.15 μm standard CMOS process. Simulation results show that the proposed BGR achieves a temperature coefficient (TC) of 0.84 ppm/°C over the temperature range from −40 °C to 120 °C with a 1.2 V supply voltage. The current consumption of proposed BGR is 51 μA at 27 °C. The line regulation of proposed BGR is 0.023%/V over the supply voltage range from 1.2 V to 1.8 V at 27 °C. In addition, the PSRRs of proposed BGR are −91 dB, −81 dB, −61 dB and −29 dB at DC or 10 Hz, 1 kHz, 10 kHz, and 100 kHz, respectively.     

衬底驱动超低压CMOS带隙基准电压源

采用二阶温度补偿和电流反馈技术,设计实现了一种基于衬底驱动技术和电阻分压技术的超低压CMOS带隙基准电压源。采用衬底驱动超低压运算放大器作为基准源的负反馈,使其输出用于产生自身的电流源偏置,其电源抑制比(PSRR)为-63.8dB。采用Hspice仿真,在0.9V电源电压下,输出基准电压为572.45mV,温度系数为13.3ppm/°C。在0.8~1.4V电源电压范围内,输出基准电压变化3.5mV。基于TSMC0.25μm2P5MCMOS工艺实现的衬底驱动带隙基准电压源的版图面积为203μm×478.1μm。     

Sub-1 V band-gap based and MOS threshold-voltage based voltage references in 0.13 µm CMOS

Portable and implantable device applications require low supply voltage reference circuits due to increasing trend for lower power requirements. Voltage references have been proposed for operation below 1 V for CMOS and a comprehensive analysis of the behavior of the different topologies is needed for ultra-low power designs, in order to select the right circuit topology for a given requirement. This work compares two major classes of voltage reference topologies: threshold voltage (V_T0)-based and (V_G0) bandgap voltage-based reference circuits. Four different topologies of voltage-reference designs with 1-V supply were designed and fabricated in 130 nm CMOS process. Monte Carlo analysis shows the variability of the references and of their temperature coefficients (TC), and the results are compared to measured samples. Simulations and measurements show that the threshold voltage-based references are more susceptible to the variations in the CMOS fabrication process.     

Reanalyzing the basic bandgap reference voltage circuit considering thermal dependence of bandgap energy

The basic bandgap reference voltage generator, BGR, is thoroughly analyzed and relations are reconstructed considering dependency of bandgap energy, E_g, to absolute temperature. The previous works all consider E_g as a constant, independent of temperature variations. However, E_g varies around 25 meV when the temperature is increased from 2 to 92 °C. In this paper the dependence of E_g to absolute temperature, based on HSPICE mosfet models in HSPICE MOSFET Models Manual (Version X-2005.09, 2005), is approximated by a third-order polynomial using Lagrangian interpolating method within the temperature range of 2–92 °C. Accurate analysis on the simplified polynomial reveals that the TC of V_BE must be corrected to ?1.72 mV/°K at 27 °C which has been formerly reported about ?1.5 mV/°K in Razavi (Design of analog CMOS integrated circuits, 2001) and Colombo et al. (Impact of noise on trim circuits for bandgap voltage references, 2007), ?2 mV/°K in Gray et al. (Analysis and design of analog integrated circuits, 2001), Leung and Mok (A sub-1-V 15-ppm/°C CMOS bandgap voltage reference without requiring low threshold voltage device, 2002), Banba et al. (A CMOS bandgap reference circuit with sub-1-V operation, 1999), and ?2.2 mV/°K in Jones and Martin (Analog integrated circuit design, 1997), Tham and Nagaraj (A low supply voltage high PSRR voltage reference in CMOS process, 1995). Another important conclusion is that the typical weighting coefficient of TC+ and TC? terms is modified to about 19.84 at 27 °C temperature from otherwise 16.76, when E_g is considered constant, and also 17.2, in widely read literatures, (Razavi in Design of analog CMOS integrated circuits, 2001). Neglecting the temperature dependence of E_g might introduce a relative error of about 20.5 % in TC of V_BE. Also, resistance and transistor size ratios, which denote the weighting coefficient of TC+ term, might be encountered to utmost 20.3 % error when the temperature dependence of E_g is ignored.