混合信号SoC中的衬底噪声耦合效应

衬底噪声耦合是深亚微米混合信号集成电路中常见的噪声干扰效应,严重地影响了模拟电路的性能。系统地阐述混合信号SoC中的衬底噪声耦合效应及其研究现状,讨论利用基于格林方程的边界元法对衬底建模的方法,并且分别从工艺、版图、电路等不同层次衬底噪声耦合效应的抑制方法与技术,同时对将来衬底噪声研究的发展方向以及新思路进行分析与讨论。     

一种混合信号集成电路衬底耦合噪声分析方法

讨论分析了混合信号集成电路衬底噪声耦合的机理,及对模拟电路性能的影响。提出了一种混合信号集成电路衬底耦合噪声分析方法,基于TSMC 0.35μm 2P4M CMOS工艺,以14位高速电流舵D/A转换器为例,给出了混合信号集成电路衬底耦合噪声分析方法的仿真结果,并与实际测试结果进行比较,证实了分析方法的可信性。     

数模混合电路衬底耦合模型研究

提出了数模混合集成电路衬底耦合噪声的一种建模方案将集成电路芯片的衬底划分为多个Voronoi图,计算各区域的R、C值,在将衬底RC网络映射到原电路网表之后,对新网表进行SPICE模拟,分析数模混合集成电路中的衬底噪声.用此模型模拟了两个数模混合集成电路的衬底耦合噪声,指出了在模拟电路关键器件周围加保护环是减少衬底耦合噪声的一种有效途径.     

单片数字锁相环衬底噪声的SPICE模拟及分析

应用PSPICE及采用C语言自编的外部程序,对单片数字锁相环中衬底噪声耦合及衬底噪声对电路性能的影响进行了模拟和分析,有助于进一步理解衬底噪声以及衬底噪声对复杂的混合信号电路工作的影响。提出了实际应用中据此选择合适的衬底类型和相应的减小衬底噪声的方法。     

一种离散点式IC衬底噪声有源抵消方法

在混合信号集成电路中,衬底耦合噪声是一个很大的问题.文章在现有噪声有源抵消电路的基础上,提出了一种新的多抵消点离散式有源噪声抵消方法.它采用有源放大器,产生负相噪声,通过若干个离散抵消点输出,与原来噪声相叠加、互相抵消,起到削弱噪声影响的作用.与原有噪声抵消电路相比,这种多抵消点离散式电路能更为显著地减小通过衬底传导的耦合噪声对模拟电路的影响,噪声幅度削减50%.     

一种面向SOC的衬底噪声宏模型

针对SOC中常见的衬底噪声耦合问题,通过将器件模拟与拟合法相结合,基于0.25 μ m CMOS工艺提取衬底结构参数建立了电阻宏模型.该模型被应用于CMOS放大器电路,利用Hspice进行仿真,仿真结果表明,该模型从时、频域角度都能较好地表征出衬底噪声对模拟电路性能的影响,对深亚微米混合信号电路设计具有重要的指导意义.     

一种CMOS混合信号电路衬底噪声耦合模型

利用二维器件模拟器MEDICI提取出重掺杂外延型衬底的电阻宏简化模型,所需的6个参数均可通过器件模拟得到,能够精确表征混合信号集成电路中的衬底噪声特性。基于0.25μm CMOS工艺所建立的电阻宏模型,设计了简单的混合信号电路进行应用验证,证明了该模型能够有效表征混合信号集成电路的衬底噪声。     

微电子文摘

1 模拟电路技术WD93501 混合信号集成电路中衬底噪声的实验结果和模拟技术=Experimental results and modetiontechnlques for substrate noise in mixed-signal integratedcircuits[刊,美]/Su,D.K.…//IEEE J.Sol.Sta.Circ.-1993,28(4).-420～430数字MOS电路中的开关瞬时电流通过衬底耦合干扰同一个管芯上集成的模拟电路。本文描述观察这种衬底噪声效应的实验技术。在由重掺杂体硅圆片上生长的外延层构成的衬底上用CMOS工艺进行实验,评估了各种减少衬底串扰的方法(采用模拟     

其它电路与技术

Y2000-62078-253 0007684在混合信号灵巧功率环境中在衬底噪声下数字电路的特性=The behavior of digital circuits under substratenoise in a mixed-signal smart-power environment[会,英]/Secareanu,R.M.& Kourtev,I.S.//1999 Inter-national Symposium on Power Semiconductor Devices andIC's.—253～256(U)叙述了在混合信号灵巧功率系统中数字电路的特性。介绍并讨论了可以解释这一过程的几个模型和机理,其中衬底噪声可影响芯片上数字电路的性能,以及数字电路的抗噪声特性。利用模拟和芯片测试数据,演示了这些模型和机理。参10     

重掺杂型混合信号集成电路衬底的噪声模型研究

应用器件模拟软件SILVACO模拟三种结构重掺杂型衬底中注入高频电流的分布,根据模拟结果分析得出重掺杂型衬底的简化模型为一单节点,进而将简化模型与实际的混合信号集成电路结合,建立起重掺杂型衬底的噪声模型,并给出了参数估算式。     

混合信号衬底耦合噪声的传播及抑制方法

介绍了衬底噪声耦合效应在不同工艺衬底中的传播,应用medici模拟了不同衬底中,噪声发生端和噪声接收端噪声在不同间距下噪声传播的情况,并从工艺和电路设计两个方面介绍了一系列抑制衬底噪声的方法。     

Efficient methods for modelling substrate coupling in mixed-signalintegrated circuits

A key problem in the design of large mixed-signal circuits is the noise caused by the coupling of digital signals into the substrate. This paper describes methods that allow circuit designers to model efficiently such substrate noise in large mixed-signal SPICE designs. In the light of these techniques a new methodology is presented for efficiently modelling the substrate noise caused by current injection and its coupling to analogue signals; this is then extended to provide a real-time modelling capability. The practicality and the numerical efficiency of the methods are demonstrated on several prototype example circuits     

Verification techniques for substrate coupling and theirapplication to mixed-signal IC design

This paper presents techniques for the analysis of substrate-coupled noise in mixed-signal integrated circuits. Advantages and limitations of some commonly employed verification techniques for substrate coupling are outlined. A preprocessed boundary element method introduced in this paper utilizes precomputed z parameters to generate an analytical model for substrate impedance in a preprocessing stage. Truncated series expansions of the analytical impedance model are used to accelerate solution of the resulting boundary element equations. A methodology that applies these fast techniques to the verification of large mixed-signal circuits and results that confirm its efficiency are described. This complete methodology has been applied to the design and verification of an industrial mixed-signal video analog-to-digital converter IC for substrate noise problems     

Substrate Noise Coupling in SoC Design: Modeling, Avoidance, and Validation

Issues related to substrate noise in system-on-chip design are described including the physical phenomena responsible for its creation, coupling transmission mechanisms and media, parameters affecting coupling strength, and its impact on mixed-signal integrated circuits. Design guidelines and best practices to minimize the generation, transmission, and reception of substrate noise are outlined, and different modeling approaches and computer simulation methods used in quantifying the noise coupling phenomena are presented. Finally, experiments that validate the modeling approaches and mitigation techniques are reviewed     

Schematic-Driven Substrate Noise Coupling Analysis in Mixed-Signal IC Designs

This paper presents an approach to reduce substrate cross-talk noise between noisy and sensitive circuitry in mixed-signal integrated circuits at different stages of design and layout development. Silencer! a new, fully automated, schematic-driven substrate noise coupling analysis tool is introduced to accomplish this task. The tool seamlessly enables substrate noise coupling analysis in a standard mixed-signal design flow. Two different methods, fast scalable macro-models and a boundary element solver are integrated into Silencer!. These methods allow extractions of a substrate network from geometric layout information. Simulation results obtained with Silencer! are accurate to within 10% of measured integrated circuits     

Substrate coupling in digital circuits in mixed-signal smart-power systems

This paper describes theoretical and experimental data characterizing the sensitivity of nMOS and CMOS digital circuits to substrate coupling in mixed-signal, smart-power systems. The work presented here focuses on the noise effects created by high-power analog circuits and affecting sensitive digital circuits on the same integrated circuit. The sources and mechanism of the noise behavior of such digital circuits are identified and analyzed. The results are obtained primarily from a set of dedicated test circuits specifically designed, fabricated, and evaluated for this work. The conclusions drawn from the theoretical and experimental analyses are used to develop physical and circuit design techniques to mitigate the substrate noise problems. These results provide insight into the noise immunity of digital circuits with respect to substrate coupling.     

Evolution of substrate noise generation mechanisms with CMOS technology scaling

Substrate noise is a major obstacle for single-chip integration of mixed-signal systems. To reduce this problem and to assess its evolution with CMOS technology scaling, the different mechanisms that generate substrate noise and their dependencies on different parameters need to be well understood. In this paper, we show that with downscaling of the technology, substrate noise due to supply coupling becomes the dominant coupling mechanism when the chip substrate is directly biased with the digital ground. With Kelvin ground substrate biasing on the other hand, source/drain capacitive coupling becomes the dominant coupling mechanism. Further, we show that with downscaling, the peak value of the supply coupling noise component becomes more dependent on the relative ratio of the switching capacitance to the nonswitching capacitance, which is formed by the circuit decoupling and the nonswitching circuit elements, rather than the Ldi/dt noise. These insights illustrated in a quantitative framework are believed to be very useful for the systematic use of digital low-noise design techniques in future CMOS technologies.     

Analytical and experimental verification of substrate noise spectrum for mixed-signal ICs

In this paper, the most relevant characteristics of the substrate noise spectrum for mixed-signal integrated circuits (ICs) are derived using a simple analytical model. These characteristics are related to parameters of the digital circuit, the package + printed circuit board parasitics, and other elements of the mixed-signal IC. The model used to derive the substrate noise spectral characteristics includes the statistical properties of the digital switching current waveform and the coupling transfer function between the digital power supply nodes and the substrate node of the victim circuitry. The results of the work are validated experimentally on a mixed-signal prototype.     

Computer-aided design considerations for mixed-signal coupling inRF integrated circuits

This paper reviews computer-aided design techniques to address mixed-signal coupling in integrated circuits, particularly wireless RF circuits. Mixed-signal coupling through the chip interconnects, substrate, and package is detrimental to wireless circuit performance as it can swamp out the small received signal prior to amplification or during the mixing process. Specialized simulation techniques for the analysis of periodic circuits in conjunction with semi-analytical methods for chip substrate modeling help analyze the impart of mixed-signal coupling mechanisms on such integrated circuits. Application of these computer-aided design techniques to real-life problems is illustrated with the help of a design example. Design techniques to mitigate mixed-signal coupling can be determined with the help of these modeling and analysis methods     

Simulation and measurement of supply and substrate noise in mixed-signal ICs

Digital noise in mixed-signal circuits is characterized using a scalable macromodel for substrate noise coupling. The noise coupling obtained through simulations is verified with measured data from a digital noise generator and noise sensitive analog circuits fabricated in the 0.35-/spl mu/m heavily doped CMOS process. The simulations and measurements also demonstrate the effectiveness of including grounded guard rings and separating bulk and supply pins in digital circuits to reduce substrate coupling.