一种应用于GNSS接收机的低噪声和低杂散频率综合器

A low phase noise and low spur phase locked loop （PLL） frequency synthesizer for use in global navigation satellite system （GNSS） receivers is proposed. To get a low spur, the symmetrical structure of the phase frequency detector （PFD） produces four control signals, which can reach the charge pump （CP） simultaneously, and an improved CP is realized to minimize the charge sharing and the charge injection and make the current matched. Additionally, the delay is controllable owing to the programmable PFD, so the dead zone of the CP can be eliminated. The output frequency of the VCO can be adjusted continuously and precisely by using a programmable LC-TANK. The phase noise of the VCO is lowered by using appropriate MOS sizes. The proposed PLL frequency synthesizer is fabricated in a 0.18 μm mixed-signal CMOS process. The measured phase noise at 1 MHz offset from the center frequency is -127.65 dBc/Hz and the reference spur is -73.58 dBc.     

GHz band frequency hopping PLL-based frequency synthesizers

In this paper we describe a full-integrated circuit containing all building blocks of a completed PLL-based synthesizer except for low pass filter（LPF）. The frequency synthesizer is designed for a frequency hopping （FH） transceiver operating up to 1.5 GHz as a local oscillator. The architecture of Voltage Controlled Oscillator （VCO） is optimized to get better performance, and a phase noise of -111.85-dBc/Hz @ 1 MHz and a tuning range of 250 MHz are gained at a centre frequency of 1.35 GHz. A novel Dual-Modulus Prescaler（DMP） is designed to achieve a very low jitter and a lower power. The settling time of PLL is 80 μs while the reference frequency is 400 KHz. This monolithic frequency synthesizer is to integrate all main building blocks of PLL except for the low pass filter, with a maximum VCO output frequency of 1.5 GHz, and is fabricated with a 0.18 μm mixed signal CMOS process. Low power dissipation, low phase noise, large tuning range and fast settling time are gained in this design.     

Low power fast settling multi-standard current reusing CMOS fractional-N frequency synthesizer

正A low power fast settling multi-standard CMOS fractional-N frequency synthesizer is proposed.The current reusing and frequency presetting techniques are adopted to realize the low power fast settling multi-standard fractional-N frequency synthesizer.An auxiliary non-volatile memory(NVM) is embedded to avoid the repetitive calibration process and to save power in practical application.This PLL is implemented in a 0.18μm technology. The frequency range is 0.3 to 2.54 GHz and the settling time is less than 5μs over the entire frequency range.The LC-VCO with the stacked divide-by-2 has a good figure of merit of-193.5 dBc/Hz.The measured phase noise of frequency synthesizer is about-115 dBc/Hz at 1 MHz offset when the carrier frequency is 2.4 GHz and the reference spurs are less than -52 dBc.The whole frequency synthesizer consumes only 4.35 mA @ 1.8 V.     

一种应用于GNSS/蜂窝网混合定位接收机的多标准频率合成器

A fully integrated hybrid integer/fractional frequency synthesizer is presented.With a single multiband voltage-controlled-oscillator(VCO),the frequency synthesizer can support GPS,Galileo,Compass and TDSCDMA standards.Design is carefully performed to trade off power,die area and phase noise performance.By reconfiguring between the integer mode and fractional mode,different frequency resolution requirements and a constant loop bandwidth for each standard can be achieved simultaneously.Moreover,a long sequence length,reduced hardware complexity multi-stage-noise-shaping(MASH).-.modulator is employed to reduce fractional spur in the fractional mode.Fabricated in a 0.18 m CMOS technology,the frequency synthesizer occupies an active area of 1.48 mm2 and draws a current of 13.4-16.2 mA from a 1.8 V power supply.The measured phase noise is lower than-80 dBc/Hz at 100 kHz offset and-113 to-124 dBc/Hz at 1 MHz offset respectively,while the measured reference spur is-71 dBc in integer mode and the fractional spur is-65 dBc in fractional mode.     

A low power fast-settling frequency-presetting PLL frequency synthesizer

This work presents the design and implementation of a 2.4 GHz low power fast-settling frequency-presetting PLL frequency synthesizer in the 0.18μm CMOS process.A low power mixed-signal LC VCO,a low power dual mode prescaler and a digital processor with non-volatile memory are developed to greatly reduce the power consumption and the setting time.The digital processor can automatically calibrate the presetting frequency and accurately preset the frequency of the VCO under process variations.The experiment...     

具有自校准压控振荡器和精确自动频率校准算法的低噪声频率合成器

A low noise phase locked loop （PLL） frequency synthesizer implemented in 65 nm CMOS technology is introduced. A VCO noise reduction method suited for short channel design is proposed to minimize PLL output phase noise. A self-calibrated voltage controlled oscillator is proposed in cooperation with the automatic frequency calibration circuit, whose accurate binary search algorithm helps reduce the VCO tuning curve coverage, which reduces the VCO noise contribution at PLL output phase noise. A low noise, charge pump is also introduced to extend the tuning voltage range of the proposed VCO, which further reduces its phase noise contribution. The frequency synthesizer generates 9.75-11.5 GHz high frequency wide band local oscillator （LO） carriers. Tested 11.5 GHz LO bears a phase noise of-104 dBc/Hz at 1 MHz frequency offset. The total power dissipation of the proposed frequency synthesizer is 48 mW. The area of the proposed frequency synthesizer is 0.3 mm^2, including bias circuits and buffers.     

一个含宽带VCO 和多模正交分频器的可输出220MHz-1100MHz 频率的低噪声频率综合器

This paper presents a low phase-noise fractional-N frequency synthesizer which provides an inphase/quadrature-phase(I/Q) signal over a frequency range of 220–1100 MHz for wireless networks of industrial automation(WIA) applications. Two techniques are proposed to achieve the wide range. First, a 1.4–2.2 GHz ultralow gain voltage-controlled oscillator(VCO) is adopted by using 128 tuning curves. Second, a selectable I/Q divider is employed to divide the VCO frequency by 2 or 3 or 4 or 6. Besides, a phase-switching prescaler is proposed to lower PLL phase noise, a self-calibrated charge pump is used to suppress spur, and a detect-boosting phase frequency detector is adopted to shorten settling time. With a 200 k Hz loop bandwidth, lowest measured phase noise is 106 d Bc/Hz at a 10 k Hz offset and 131 d Bc/Hz at a 1 MHz offset. Fabricated in the TSMC 0.18 m CMOS process, the synthesizer occupies a chip area of 1.2 mm2, consumes only 15 m W from the 1.8 V power supply,and settles within 13.2 s. The synthesizer is optimized for the WIA applications, but can also be used for other short-range wireless communications, such as 433, 868, 916 MHz ISM band applications.     

具有自动频率校准的宽频率范围Σ-Δ小数频率综合器

A wide range fractional-N frequency synthesizer in 0.18μm RF CMOS technology is implemented. A switched-capacitors bank LC-tank VCO and an adaptive frequency calibration technique are used to expand the frequency range.A 16-bit third-order sigma-delta modulator with dither is used to randomize the fractional spur. The active area is 0.6 mm~2.The experimental results show the proposed frequency synthesizer consumes 4.3 raA from a single 1.8 V supply voltage except for buffers.The frequency range is 1.44-2.11 GHz and the frequency resolution is less than 0.4 kHz.The phase noise is -94 dBc/Hz @ 100 kHz and -121 dBc/Hz @ 1 MHz at the output of the prescaler with a loop bandwidth of approximately 120 kHz.The performance meets the requirements for the multi-band and multi-mode transceiver applications.     

一种基于环形振荡器的双环路锁相环

A dual-loop phase-locked loop（PLL）for wideband operation is proposed.The dual-loop architecture combines a coarse-tuning loop with a fine-tuning one,enabling a wide tuning range and low voltage-controlled oscillator（VCO）gain without poisoning phase noise and reference spur suppression performance.An analysis of the phase noise and reference spur of the dual-loop PLL is emphasized.A novel multiple-pass ring VCO is designed for the dual-loop application.It utilizes both voltage-control and current-control simultaneously in the delay cell. The PLL is fabricated in Jazz 0.18-μm RF CMOS technology.The measured tuning range is from 4.2 to 5.9 GHz.It achieves a low phase noise of–99 dBc/Hz@1 MHz offset from a 5.5 GHz carrier.     

A 8.75-11.2-GHz,low phase noise fractional-N synthesizer for 802.11a/b/g zero-IF transceiver

An ultra broadband fractional-N frequency synthesizer for 802.11a/b/g zero-IF transceiver application is presented.The mathematical models for the behavior of the synthesizer’s spur and phase noise are analyzed,and the optimization methodology is proposed.Measurement results exhibits that the frequency synthesizer’s integrated phase noise is less than 1°(1 kHz to 100 MHz)with a 4.375 GHz carrier(after divide-by-2),and the reference frequency spur is below-60 dBc operating with a 33 MHz reference clock.The frequency synthesizer is fabricated on a standard 0.13μm RF CMOS process and consumes 39.6 mW from a 1.2 V supply voltage.     

A fast-settling frequency-presetting PLL frequency synthesizer with process variation compensation and spur reduction

This paper proposes a fast-settling frequency-presetting PLL frequency synthesizer.A mixed-signal VCO and a digital processor are developed to accurately preset the frequency of VCO and greatly reduce the settling time.An auxiliary tuning loop is introduced in order to reduce reference spur caused by leakage current.The digital processor can automatically compensate presetting frequency variation with process and temperature,and control the operation of the auxiliary tuning loop.A 1.2 GHz integer-N synthesizer with 1 MHz reference input Was implemented in a 0.18μm process.The measured results demonstrate that the typical settling time of the synthesizer is less than 3μs,and the phase noise is-108 dBc/Hz@1MHz.The reference spur is-52 dBc.     

A 2.4 GHz 6.6 mA fully differential CMOS PLL frequency synthesiser

A 2.4 GHz 6.6 mA fully differential CMOS phase-locked loop (PLL) frequency synthesiser with an on-chip capacitance-calibrated loop filter is presented. The frequency synthesiser includes a differential-tuning voltage-control oscillator (VCO) and a fully differential charge-pump (CP) to reject the common-mode noise. A combination of analogue tuning and digital tuning techniques (4-bit binary weighted capacitor array) is utilised to extend the tuning range of the VCO. A novel topology and an optimisation strategy are utilised to reduce the power consumption of the frequency divider. The capacitance in the loop filter is on-chip calibrated so that the loop dynamic characteristics are accurately controlled despite the process variation. The frequency synthesiser has been implemented in UMC 0.18 μm CMOS. The measured results show that the VCO achieves a 29% tuning range, from 2.056 to 2.758 GHz. The phase noise of the frequency synthesiser is ? 117.2 dBc/Hz at 1 MHz frequency offset from the 2.3 GHz carrier. The settling time is less than 50 μs, and the capacitance in the loop filter could be on-chip calibrated to ±3.9% precision. The whole frequency synthesiser only consumes 6.6 mA current from a 1.8 V power supply.     

使用三位三阶Δ∑调制器的集成1GHz小数频率合成器

本文实现了一个采用三位三阶Δ∑调制器的高频谱纯度集成小数频率合成器.该频率合成器采用了模拟调谐和数字调谐组合技术来提高相位噪声性能,优化的电源组合可以避免各个模块之间的相互干扰,并且提高鉴频鉴相器的线性度和提高振荡器的调谐范围.通过采用尾电流源滤波技术和减小振荡器的调谐系数,在片压控振荡器具有很低的相位噪声,而通过采用开关电容阵列,该压控振荡器达到了大约100MHz的调谐范围,该开关电容阵列由在片数字调谐系统进行控制.该频率合成器已经采用0.18μm CMOS工艺实现,仿真结果表明,该频率频率合成器的环路带宽约为14kHz,最大带内相位噪声约为-106dBc/Hz;在偏离载波频率100kHz处的相位噪声小于-120dBc/Hz,具有很高的频谱纯度.该频率合成器还具有很快的反应速度,其锁定时间约为160μs.     

一个自调谐,自适应的1.9GHz分数/整数频率综合器

本文提出了一个具有自调谐,自适应功能的1.9GHz的分数/整数锁相环频率综合器.该频率综合器采用模拟调谐和数字调谐相结合的技术来提高相位噪声性能.自适应环路被用来实现带宽自动调整,可以缩短环路的建立时间.通过打开或者关断 ΣΔ 调制器的输出来实现分数和整数分频两种工作模式,仅用一个可编程计数器实现吞脉冲分频器的功能.采用偏置滤波技术以及差分电感,在片压控振荡器具有很低的相位噪声;通过采用开关电容阵列,该压控振荡器可以工作在1.7GHz~2.1GHz的调谐范围.该频率综合器采用0.18 μ m,1.8V SMIC CMOS工艺实现.SpectreVerilog仿真表明:该频率综合器的环路带宽约为100kHz,在600kHz处的相位噪声优于-123dBc/Hz,具有小于15 μ s的锁定时间.     

Digital Coarse Tuning Loop for Wide-Band Fast-Settling Dual-Loop Frequency Synthesizers

提出了一种用于宽带、双环路频率综合器的粗调环路结构.该粗调环路由数字电路设计实现,包含逐次逼近寄存器和新结构的频率比较单元两个模块.其中,频率比较单元在一定的参考时间内对预分频器的输出信号周期进行计数,然后通过比较计数结果与预设值的大小来估计VCO输出频率.对比较误差进行了详细分析,分析表明,在一定的比较时间内该结构的比较误差比现有结构小20倍,而且由于重复利用可编程分频器作为粗调环路的一部分,整体电路也大为简化.     

快速锁定、宽带双环路频率综合器的数字粗调环路

提出了一种用于宽带、双环路频率综合器的粗调环路结构.该粗调环路由数字电路设计实现,包含逐次逼近寄存器和新结构的频率比较单元两个模块.其中,频率比较单元在一定的参考时间内对预分频器的输出信号周期进行计数,然后通过比较计数结果与预设值的大小来估计VCO输出频率.对比较误差进行了详细分析,分析表明,在一定的比较时间内该结构的比较误差比现有结构小20倍,而且由于重复利用可编程分频器作为粗调环路的一部分,整体电路也大为简化.     

A digital approach to an FM exciter

A digital approach to an FM exciter is presented that provides several advantages over previous analog techniques. This approach, called direct digital frequency modulation (DDFM), is centered around a direct digital synthesis (DDS) chip which allows true digital generation of the FM signal. The DDS chip is a perfectly linear modulator with superior phase-noise characteristics over the current analog voltage-controlled oscillator (VCO) approach. The DDS modulator drives a low-noise phase-locked loop (PLL) which allows upconversion to any FM channel without manual tuning. The exciter demonstrates superior microphonics immunity by separating the frequency tuning from the modulation path, thus allowing wider PLL bandwidths. The exciter can accept either the existing composite analog format or can interface with future digital sources     

A 3.5-GHz PLL for fast low-IF/zero-IF LO switching in an 802.11 transceiver

A PLL technique is introduced that enables fast and accurate frequency switching, independent of the loop bandwidth. It uses separate tuning paths, each driving a separate VCO tune port. Different frequencies are produced by letting the VCO make different weighted combinations of the stable tuning voltages. The PLL converges to the stable tuning voltages by switching it a few times between the desired frequencies and tuning paths. Once the stabilized tuning voltages are found, one can switch between frequencies as fast as one can switch between K/sub VCO/s. The technique is applied to a 3.5-GHz integer-N PLL to enable fast jumping of the local oscillator (LO) frequency when an 802.11 transceiver is switched between a low and a zero intermediate frequency (LIF/ZIF). It uses dual phase/frequency detectors (PFD), charge pumps (CPs), and on-chip loop filters to control two separate low-leakage VCO tune ports. Each PFD/tune port combination can be (de)activated separately, without disturbing the loop filters' charge. The 50-kHz bandwidth PLL achieves a measured 7-MHz jump with /spl plusmn/20 kHz accuracy within 6 /spl mu/s. The measured phase noise is -123 dBc/Hz at 1-MHz offset.     

VCO电调特性的线性校正技术综述

VCO电调特性的线性校正技术是决定线性调频连续波雷达系统性能的关键技术之一。给出了VCO电调线性度的基本定义。VCO电调特性的线性校正技术主要包括电抗补偿线性校正、开环线性校正和闭环线性校正三种基本校正方案。详细分析了各种校正方案的基本原理,并对各种校正方案的优缺点进行了对比分析;同时,详细介绍了VCO线性校正技术的最新研究进展。