一种71dB动态范围的低功耗可编程增益放大器

本文实现了一款应用于电力线通信的可编程增益放大器(PGA)。采用闭环直接耦合方式,动态范围为71dB,调节精度为1dB。为了优化功耗和面积,本文提出了一种新的电阻阵列。该设计在SMIC0.18μm工艺下仿真,结果表明:在35dB增益下输入参考噪声为20nV/姨Hz;输出电压峰峰值为1V时,THD达到-68dB;最大增益误差为0.11dB;在1.8V的供电电压下,功耗为1mA。     

一种用于预放大器的平均电阻网络设计

基于预放大器阵列,设计了一种用于解决电压失调的平均电阻网络。分析了电阻网络边界效应产生的原因。采用冗余预放大器设计、环形平均网络设计,并提出非等值终端电阻设计缓解边界效应。提出节点矩阵电流方程,为平均电阻网络的设计提供优化方向。在采用节点矩阵电流方程改善边界效应后,将该预放大器阵列用于12 bit的折叠插值ADC中,在2.5 GSPS采样频率、1.242 GHz的0.8 V正弦输入下,得到ADC的ENOB为10.32 bits,SFDR为74.3 dB。     

电阻网络元模拟算法及其在IC设计中的应用

提出了一种模拟任意形状的薄层电阻的方法－－电阻网络元模拟算法。将模拟值和计算值进行比较表明，该方法具有精度高和操作简单的优点，从而在ＩＣ的设计中获得广泛的应用。     

基于平面埋阻工艺的Wilkinson功分网络设计

针对低剖面易集成的功分网络需求,介绍了一种基于平面埋阻工艺的K频段(19.5～21.5 GHz)的Wilkinson功分器的设计与测试方法。设计中采用埋入式Ni-P电阻材料,通过电阻层与带状线中间层集成,减小功分网络厚度。通过优化仿真,加工了一款1分16平面埋阻Wilkinson功分网络。测试夹具与功分网络的互联采用毛纽扣弹性压接方式,实现射频信号垂直互联。经测试验证,此网络的幅相均方根误差分别控制在0.4 dB和5°以内,实际插入损耗可控制在14 dB以内。     

基于多β晶体管和新颖电阻网络的高速D／A转换器

本文通过对Ｄ／Ａ转换器权电阻网络和Ｔ型电阻网络的分析,提出了一种新颖的电阻转换网络。该网络比Ｔ型电阻网络节省四分之一电阻数量,可保证较高的转换精度。该网络结合多β晶体管构成的电压主型模拟开关实现了超高速Ｄ／Ａ转换器的新设计,计算机模拟表明该Ｄ／Ａ转换器具有正确的逻辑功能,工作速度极快。     

超高速VLSI中多晶硅发射极晶体管串联电阻的测量

本文对目前流行的测量晶体管串联电阻的常规方法进行了理论分析和实验验证，结果表明，用常规方法测量多晶硅发射极晶体管串联电阻的误差很大。     

氧化限制型垂直腔面发射激光器串联电阻分析

含氧化限制孔的VCSEL具有低的阈值电流，但氧化孔的存在也会加大串联电阻．本文采用理论模型，详细计算了氧化限制型VCSEL的串联电阻．把串联电阻分解为垂直方向电阻和横向电阻，分析了串联电阻与氧化孔半径的关系，提出了降低VCSEL串联电阻的具体方法．     

一种低电源电压曲率补偿带隙基准

设计了一个在0.8μm BiCMOS工艺、低于1 V电源电压下的带隙基准电压源,能稳定产生0.61 V的基准电压。该电路结合当今电压基准主流技术及研究进展,采用了一种系统失调仅912μV的新型运算放大器;采取了T型电阻网络和加入曲率补偿支路的方法,实现了大于59 dB电源抑制比和-30~150℃范围内11.7 ppm/℃的温度系数。     

薄膜电阻网络稳定性和可靠性研究

本文通过对薄膜电阻网络稳定性和可靠性的研究，分析了影响薄膜电阻网络稳定性和可靠性的因素。通过在蒸发过程中合理地控制几个关键工艺参数、选择合适的热处理条件等方法，能够实现电阻网络长期稳定性和可靠性的提高。     

权电流型D/A转换器的设计

权电流网络用于克服电阻网络D／A转换器中模拟开关的导通电阻和导通压降。利用倒Ⅱ型电阻网络设计了一种新颖的权电流型D／A转换器。相比由倒T型电阻网络组成的权电流型D／A转换器，该电路具有明显的优点，使其在电子技术应用领域有重要的现实意义和实用价值。     

Kelvin四线连接电阻测试技术及应用

介绍了开尔文(Kelvin)四线连接方式测试电阻的原理,针对复杂电阻网络提出电阻隔离测试技术.分析了采用全开尔文更精确测量极小电阻的方法,介绍了在特殊情况下使用分离开尔文连接测试电阻的方法和用途.     

电阻悬浮的MEMS热膜式气体流量传感器设计

设计了一种新型电阻悬浮结构的热膜式气体流量传感器,具有测量精度高、灵敏度好、抗压能力强、微加工工艺简单等特点。采用ANSYS软件对传感器芯片在不同流速下的温度场进行了有限元仿真,得出了上下游温差与流速的关系曲线。通过比较热膜电阻非悬浮与悬浮时的导热损失和压力分布,得到了将热膜电阻悬浮的流量传感器的性能要优于一般传感器的结论,其灵敏度为一般传感器的3.6倍。分析表明,传感器的响应时间仅为0.17 ms,比一般传感器快了好几倍;流速在0～0.5 m/s和0.5～2.5 m/s时,传感器输出信号都有较好的线性度,使其能够应用于小流量和大流量的测量当中;流道高度为150μm时,流量为0～2.7 L/h。根据工艺条件和仿真结果,确定了传感器芯片的结构尺寸和微加工工艺流程。     

基于厚膜混合集成电路的激光调阻工艺研究

激光调阻具有高精度、高效率等特点,是目前厚膜混合集成电路最为常用的电阻修调方法。为了实现厚膜混合集成电路中精度电阻的制作,文章对激光调阻工艺进行了系统研究,内容包括探针卡焊接组装、调阻程序编制以及工艺试验研究。通过进行试验验证,选用L型调阻路径,调阻精度已达到±0.5%,满足设计要求。     

Novel universal current-mode filters using unity-gain cells

Two novel universal current-mode filters using unity-gain current followers (CFs) and voltage followers (VFs) are presented. The first one, employing three CFs, one VF, two grounded capacitors and two resistors, has two inputs and three outputs. The second one, employing only two CFs, one VF, two grounded capacitors and two resistors, has four inputs and a single output. Both proposed circuits oOEer the following advantageous features: universal current-mode filter realization from the same configuration, no requirements of component matching conditions, employment of two grounded capacitors ideal for integration, employment of two virtually grounded resistors good for voltage control, easy adjustment of ω₀/Q and ω₀ through separate virtually grounded resistors and low active and passive sensitivity performance.     

Meander-channel c.c.d. (m.c.c.d.) recursive filter

A modified input-weighting concept for a c.c.d. recursive filter is proposed; it has been implemented using an m.c.c.d. with a complementary input scheme which provides net weighting coefficients. This improved structure requires neither operational amplifiers nor resistors. The operation and performance of the fabricated 2nd-order bandpass filter are presented.     

多挡分压器的分析与设计

通过理论分析和公式推导,本文研究了基本固定电阻分压器、电容补偿分压器和并接式、串接式、链接式多挡分压器的特点。通过研究L型和定阻型等比电阻分压器的设计问题,给出了设计常用等比分压器的两个关键参数表。表格提供了L型分压器需要计算的3种计算公式及电阻和定阻型分压器需要计算的4种电阻的计算公式,为等比分压网络中电阻值的计算提供了方便。误差分析表明,对于n级链接式分压器,其总的设计误差约为各级误差之和。     

Topological Considerations for the Diagnosability Conditions of Analogue Circuits Using a Pair of Conjugate Trees

The idea of using topological conditions in the analysis of nonlinear circuits has attracted the attention of researchers in recent years. This paper introduces a method that foccusses on the problem of analogue circuit diagnosis. The method determines the topological conditions for assessing the diagnosability of analogue circuits by resorting to the pair of conjugate trees. The method deals with circuits containing V–resistors, I–resistors, independent current and voltage sources, nullators and norators. More active elements can also be included by using appropriate models based on nullator and norator schemes.     

On the numerical errors induced by the space-time discretization in the LE-FDTD method

In this work, the accuracy of the lumped element finite-difference time-domain (LE-FDTD) method is discussed in the particular case of a planar distribution of equal resistors. Following the von Neumann technique and assuming a uniform grid, the effective impedance of the lumped resistor has been rigorously derived in a closed form. The result obtained has been compared with the LE-FDTD simulation of a simple test structure. This structure consists of an infinitely long parallel-plate waveguide loaded with the planar distribution of resistors. The excellent agreement obtained validates the approach showing a dependence of the effective resistor impedance on spatial and temporal discretization steps.     

Calculation of the resistance value of laser-trimmable planar resistors in an interactive mask-layout design system

The calculation method is especially suited for diffused resistors in integration processes and metal-film resistors in thin-film processes which can be adjusted by laser trimming. The method is based on a special application of Green's boundary formula. By modeling the resistor in a special way, the potential problem is reduced to a single-boundary problem. As a consequence, the calculation time and the necessary computer memory are reduced while the accuracy reduction remains small in practical cases. Therefore, the calculation can be carried out on a small computer, making interactive computer design of laser-trimmable resistors on IC layouts more feasible and less expensive. The computing time typically amounts to a few seconds. The method is illustrated by practical examples.