2位GaAs超高速模-数转换电路的设计与制作

模数(A-D)转换电路是信号处理系统中的一种关键性元件。本文结合现有GaAs起高速集成电路工艺,提出了一种2位GaAs A-D转换电路的设计方法,并制作出了单片形式的2位GaAs A/D转换电路。实验结果表明,该电路能正常工作在1Gs/s的转换速率下。它的转换时间小于1.0ns,电路功耗不高于340mW。这说明它在速度和功耗方面已展现出比Si双极电路更为广阔的发展前景。     

GaAs基E/D PHEMT技术单片集成微波开关及其逻辑控制电路

利用GaAs基 E/D PHEMT 技术单片集成微波开关及其逻辑控制电路的制作工艺和设计方法,采用0.8μm GaAs E/D PHEMT工艺,制备出性能良好的解码器功能内置的DC~10GHz SPDT MMIC,基本实现逻辑电路与开关电路的集成. 开关电路在DC~10GHz内插入损耗小于1.6dB,隔离度大于24dB;整个电路只需要1位控制信号,有效地减少了开关电路的控制端口数目,节省了芯片面积,为GaAs多功能电路的研究奠定了基础.     

HP3458A81／2位数字式万用表中的A／D转换器

HP3458A8(1 / 2)位数字式万用表对A/D转换器的性能要求较高,它的自校功能要求A/D转换器分辨率达到8(1/2)位数字,积分线性度达到7(1/2)位数字,数字交流功能要求分辨率在18bit时读数速度为50000次/秒。为此HP3458A中A/D转换器采用改进的多斜率技术,使读数速度、分辨率和积分线性度都有很大提高。分辨率为16bit时的读数速度为100000次/秒。输入跟踪的偏差小于0.1ppm。一、多斜率A/D转换技术 (一)双斜率A/D转换技术双斜率技术是一种较为简单的积分式A/D转换技术。图1所示的是实现双斜率A/D转换的一种简单电路。     

GaAs基E/D PHEMT技术单片集成微波开关及其逻辑控制电路

利用GaAs基E/D PHEMT技术单片集成微波开关及其逻辑控制电路的制作工艺和设计方法,采用0.8μm GaAsE/D PHEMT工艺,制备出性能良好的解码器功能内置的DC～10GHz SPDT MMIC,基本实现逻辑电路与开关电路的集成.开关电路在DC～10GHz内插入损耗小于1.6dB,隔离度大于24dB;整个电路只需要1位控制信号,有效地减少了开关电路的控制端口数目,节省了芯片面积,为GaAs多功能电路的研究奠定了基础.     

千兆以太网卡芯片A/D转换电路的设计与实现

介绍了一种用于千兆以太网卡芯片的8位125 MS/s CMOS流水线A/D转换电路的设计,包括体系结构设计、电路设计与仿真、版图设计。该A/D转换电路经过TSMC 0.13μm 1P8MCMOS工艺验证,工作电压为1.5 V/2.7 V。芯片测试结果表明,设计的A/D转换电路能够满足千兆以太网卡芯片的性能要求。     

一种10位40 MHz两步式A/D转换器

提出了一种基于两步转换法(5 6)的高速高精度A/D转换器体系结构,其优点是可以大幅度降低芯片的功耗及面积。采用这种结构,设计了一个10位40 MHz的A/D转换器,并用0.6μm BiCMOS工艺实现。经过电路模拟仿真,在40 MHz转换速率,1 V输入信号(Vp-p),5 V电源电压时,信噪比(SNR)为63.3 dB,积分非线性(INL)和微分非线性(DNL)均小于10位转换器的±0.5 LSB,电源电流为85.4 mA。样品测试结果:SNR为55 dB,INL和DNL小于10位转换器的±1.75 LSB。     

一种3.3 V 9位50 MS/s CMOS流水线A/D转换器

设计了一种3.3 V 9位50 MS/s CMOS流水线A/D转换器。该A/D转换器电路采用1.5位/级,8级流水线结构。相邻级交替工作,各级产生的数据汇总至数字纠错电路,经数字纠错电路输出9位数字值。仿真结果表明,A/D转换器的输出有效位数(ENOB)为8.712位,信噪比(SNR)为54.624 dB,INL小于1 LSB,DNL小于0.6 LSB,芯片面积0.37 mm2,功耗仅为82 mW。     

高精度ADC转换核的设计

在DSP的A/D转换电路中,转换核电路是整个电路的核心模块,包括时钟电路、采样保持电路（S/H）、MDAC电路、比较器电路、子ADC译码电路、冗余位数字校正电路等。同时转换核电路通常又是整个A/D电路中功耗最大的模块,其性能直接决定了整个A/D转换器的性能。文章介绍了一种l2位25MS/s转换核电路设计。该电路采用TS...     

基于80C196的高精度、低成本A/D转换

介绍了一种基于80C196单片机的A/D转换硬件电路和软件实现,利用80C196自带的10位A/D转换器和PWM输出及简单外围电路,实现了高精度、高速A/D转换。该方法同时具有成本低、实用性强等特点。     

一种低成本比较式高速A/D转换方案

提出了一种基于比较式的高速A/D转换设计方案.通过n个高速模拟比较器和n+1个高速运算放大器实现n位分辨率的高速A/D转换,达到近似于并行比较式A/D转换的速度,具有电路结构简洁、低功耗、高性价比等特点.     

A 12-bit 1-Gword/s GaAs digital-to-analog converter system

The circuitry for a 12-b 1-Gword/s digital-to-analog converter (DAC) IC is described. A DC linearity of /spl plusmn/1/8 LSB has been preserved with this all-depletion GaAs MESFET chip. Dynamic measurements in the frequency domain indicate nonlinearities of less than -62 dBc at a 1-GHz clock rate. The DAC uses a very fast FET analog current switch that exhibits sufficiently low leakage currents for a 12-b linearity. The limited on-chip matching capabilities require the precision DC currents to be generated external to the GaAs chip. A current-switching DAC that partitions the high-speed functions onto a single GaAs chip while the high-precision bit currents are realized off-chip is described. The GaAs chip contains 12 1-b cells, each of which switches an analog bit current into a single sampler circuit that is shared by all the switches. The sampler is used to increase the dynamic linearity in the DAC.     

2Gbps GaAs单片4bit数模转换器的设计与实现

详述了单片超高速2G bps G aA s 4b it数模转换器(DAC)的设计、制造及测试。在南京电子器件研究所标准76 mm G aA s工艺线采用0.5μm全离子注入M ESFET工艺完成流片。芯入输入输出阻抗实现在片50Ω匹配。4 b it DAC的微分非线性(DN L)为±0.22最低有效位(LSB),积分非线性(IN L)为±0.45LSB,达到5.2 b it的转换精度。该单片电路提供差分互补输出,长周期输出特性无漂移。其最高转换速率可达2 G bps,建立时间小于250 ps,电路核心部分功耗为110 mW。     

单片GaAs 3bit相位DAC的设计与实现

详细论述了用于数字射频存储器系统的单片超高速GaAs 3bit相位DAC的设计、制造及测试.在南京电子器件研究所标准75mm GaAs工艺线采用0.5μm全离子注入MESFET工艺完成流片.芯片输入输出阻抗实现在片50Ω匹配.测试结果表明,其工作带宽大于1.5GHz,相位精度小于4%,电路的码流翻转速率大于12Gbps.     

相位体制数模转换器动态参数的表征与测试

详细分析并讨论了相位体制数模转换器(DAC)动态参数的表征方法,提出用无杂散动态范围(SFDR)、近区谐波失真(TH D 6)、有效工作带宽(EW B)、输出信号功率及正交输出信号幅度一致性来全面描述相位DAC的频域性能。采用上述方法对利用南京电子器件研究所标准76 mm G aA sM ESFET全离子注入工艺流片得到的3b it相位DAC进行了频域测试。结果显示其EW B大于1.5 GH z,转换速率大于12 G bps,全频带内输出信号的正交精度低于4%,幅度一致性低于26%(大多数测试点低于10%)。在500 MH z输入信号下,其SFDR、TH D 6分别为33.8 dB c-、33.7 dB c。该相位DAC的动态参数良好,尤其正交性能优异。     

A 1.6-GS/s 12-bit return-to-zero GaAs RF DAC for multiple Nyquist operation

A 12-bit 1.6-GS/s digital-to-analog converter (DAC) implemented with 4-/spl mu/m/sup 2/ GaAs HBT process is presented. Return-to-zero (RZ) current switches are added to current steering DAC for high-frequency wideband applications to achieve 800-MHz bandwidth at first and second Nyquist band without the need for a reverse sinc equalization filter in wideband transmitter application. The RZ circuit also improves spectral purity by screening the switching noise from the analog output during data transition. Measured performance shows two-tone third-order harmonic distortion of -70 dB at 1.5-GHz output frequency, clocked at 1.6 GHz. Reliable interface with CMOS logic IC is guaranteed with the inclusion of a four-clock-deep FIFO circuit. The DAC dissipates 1.2 W at -5 V when sampled with 1.6-GHz clock, with typical output voltage swing of 1.2 V/sub PP/.     

12bit高稳定性数模转换器设计

设计了一款12 bit高稳定性控制类数模转换器(DAC),该DAC集成了带有稳定启动电路的新型低失调带隙基准源(BGR),改善了基准电路的稳定性以及对温度和工艺的敏感性;DAC采用了改进的两级电阻串结构,通过开关电阻匹配和特殊版图布局,在既不增加电路功耗又不扩大版图面积的前提下,提高了DAC的精度并降低了工艺浓度梯度对整体性能的影响.基于CSMC 0.5 μm 5 V 1P4M工艺对所设计的DAC芯片进行了流片验证.测试结果表明:常温下DAC的微分非线性(DNL)小于0.45 LSB,积分非线性(INL)小于1.5 LSB,并且在-55～125℃内DNL小于1 LSB,INL小于2.5 LSB;5V电源电压供电时功耗仅为3.5 mW,实现了高精度、高稳定性的设计目标.     

A stereo multibit ΣΔ DAC with asynchronous master-clockinterface

A two-channel multibit ΣΔ audio digital-to-analog converter (DAC) with on-chip digital phase-locked loop and sample-rate converter is described. The circuit requires no over-sampled synchronous clocks to operate and rejects input sample clock jitter above 16 Hz at 6 dB/octave. A second-order modulator with a multibit quantizer, switched-capacitor (SC) DAC, and single-ended second-order SC filter provides a measured out-of-band noise of -63 dBr with less than 0.1° phase nonlinearity. Measured S/(THD+N) of the DAC channel including a 0-63 dB, 1 dB/step attenuator is greater than 90 dB unweighted. The circuit is implemented in 0.6-μm DPDM CMOS, dissipating 220 mW at 5 V. Die size is 3 mm×4 mm     

A low-Voltage 10-bit CMOS DAC in 0.01-mm/sup 2/ die area

A low-voltage 10-bit digital-to-analog converter (DAC) for static/dc operation is fabricated in a standard 0.18-/spl mu/m CMOS process. The DAC is optimized for large integrated circuit systems where possibly dozens of such DAC would be employed for the purpose of digitally controlled analog circuit calibration. The DAC occupies 110 /spl mu/m/spl times/94 /spl mu/m die area. A segmented R-2R architecture is used for the DAC core in order to maximize matching accuracy for a minimal use of die area. A pseudocommon centroid layout is introduced to overcome the layout restrictions of conventional common centroid techniques. A linear current mirror is proposed in order to achieve linear output current with reduced voltage headroom. The measured differential nonlinearity by integral nonlinearity (DNL/INL) is better than 0.7/0.75 LSB and 0.8/2 LSB for 1.8-V and 1.4-V power supplies, respectively. The DAC remains monotonic (|DNL|<1 LSB) as INL reaches 4 LSB down to 1.3-V operation. The DAC consumes 2.2 mA of current at all supply voltage settings.     

Phase-domain fractional-N frequency synthesizers

The concept of phase-domain fractional-N frequency synthesis is presented. Synthesizers using this architecture can achieve fast frequency switching without limiting the minimum channel spacing. In this architecture, a numerical phase comparator is used in conjunction with weighting coefficients, as a linear weighted phase-frequency detector. The synthesizer output spur level is determined by two factors. Namely, the delay of the numerical phase comparator, and the accuracy of the digital-to-analog convertor (DAC) used to convert the phase error to the analog domain. A novel second-order timing-error cancelation scheme is proposed to eliminate the effect of the phase comparator delays. Using this technique together with a 10-bit accuracy DAC, a maximum spur level of less than -65 dBc is simulated for a 900-MHz synthesizer. The settling time of the simulated synthesizer is less than 7 /spl mu/s, and is independent of the channel spacing. The details of the synthesizer architecture, design considerations, and system-level simulations are presented. Implementation issues including the DAC accuracy and timing-error effects are discussed extensively throughout the text.     

高速GaAs ADC与GaAs DAC研制现状

本文叙述了高速GaAs ADC与GaAs DAC的研制现状。着重介绍了在芯片上有T/H电路的闪光型ADC和在芯片上有电流源的DAC,以及它们的性能。