基于Matlab的数字中频GPS信号生成模型

精确的GPS信号生成器是测试与评价先进GPS接收机设计的重要分析工具。本文在中频GPS信号理论模型分析的基础上,用Matlab实现了一种数字GPS信号生成模型,它能够在数字中频上产生GPS接收信号,其中包含仿真的噪声和接收机时钟误差。与常规的GPS信号生成器(或模拟器)相比,这种模型设计灵活、易于使用,此外,模型构建涉及对GPS信号在接收机射频前端处理过程的仿真,从而为GPS接收机射频前端的设计提供了支持。     

星载GPS接收机射频前端设计与实现

为适应星载GPS接收机的多普勒高动态范围、强射频干扰信号的空间环境,分析了射频前端的结构及MAX2769的结构特点和工作原理,利用MAX2769及少量外围电路设计实现了一种星载GPS接收机射频前端方案。测试表明,射频前端输出的数字中频信号符合设计要求,可用于基带信号处理模块,实现卫星信号捕获。其集成度高,性能优越,价格合理,适合航天工业应用。     

GPS射频信号源的设计与实现

在研究GPS信号结构的基础上,给出了GPS射频信号源的设计方案,并分模块进行了设计与实现.实验结果表明,基带/中频模块实现了GPS信号的BPSK调制和扩频调制,输出数字中频信号;射频模块实现了上变频功能,完成了信号的射频调制.     

ADF4360—4原理及其在GPS信号源中的应用

通过分析频率合成器ADF4360—4的工作原理、性能特点及其典型应用,提出一种以FPGA芯片和频率合成器ADF4360—4为核心的GPS信号源系统,给出了总体及模块设计方案,并分模块进行了设计与实现。测试结果表明,以FPGA芯片为核心的基带／中频模块完成了GPS信号的BPSK调制和扩频调制,实现了GPS数字中频信号输出;以频率合成器ADF4360—4为核心的射频模块完成了上变频功能,实现了信号的射频调制。     

GPS软件接收机基带信号处理研究

GPS软件接收机相对传统硬件接收机,设计灵活,能够迅速分析、仿真、实现各类算法.本文主要针对GPS L1频率的C/A码信号,设计并实现了GPS软件接收机的基带处理部分,阐述了射频前端原理、并行码相位搜索捕获策略以及鉴频辅助跟踪环路,并推导了适应动态环境的三阶数字环路滤波器.仿真数据和实际中频数据测试表明:算法性能优越,能迅速捕获并锁定信号,获取导航数据.     

甚高频(VHF)跳频电台接收模块的设计与实现

通过对甚高频(VHF)跳频电台射频前端接收模块设计指标和具体结构的介绍,对整个接收机射频前端电路进行了电路设计,构建了一个由第一、第二级混频器,中频放大器,第一、第二中频晶体滤波器,限幅器和推动器,正交检测器,收基带信号(RXBB)放大器,机内测试电路(BITE)以及静噪单音检测组成的接收模块电路。实验结果表明,所设计的接收模块的性能指标达到了系统设计要求,并有所提高。     

基于GP2015的GPS射频前端电路ADS优化设计

根据“超外差”结构设计了一种以GP2015为核心的GPS射频前端接收电路,混频级数设计为3级,混频输出的中频信号进行多次优化滤波。首先利用ADS2008系统建模和行为级功能仿真验证系统可行性,其次选择合适的低噪声放大器对射频信号进行放大,提高了接收机的接收灵敏度,最后对PCB板的线宽进行阻抗匹配、电路制作及电路滤波优化。测试结果表明,该电路成功地实现了射频信号的下变频及接收,输出信号功率达到-3.3 dBm,镜像抑制能力达到37 dB。     

数字阵列雷达数字收发ASIC芯片设计

数字收发电路主要功能为实现模拟中频/射频信号到数字基带信号的变换以及利用数字合成方式产生模拟中频/射频信号,广泛应用于通信和雷达的收发系统中,低功耗、高集成的数字收发电路设计也一直是数字阵列雷达数字T/R组件设计中的一个关键技术。文章介绍了一种具有完全自主知识产权的单片雷达数字收发ASIC芯片的前端设计,包括芯片结构设计、各子模块设计(ADC/DAC/DDC/DDS),给出了设计及仿真结果,该芯片在SMIC 0.18微米工艺下成功流片,经测试,芯片指标达到设计要求。     

数字阵列雷达数字下变频器ASIC芯片设计

数字下变频器主要是实现数字中频／射频信号到基带信号的变换,广泛应用于通信和雷达的数字化接收机设计中,多通道可编程DDC由于在小型化以及通道一致性方面的优势,也成为新型全数字阵列雷达数字T／R组件设计中的一个关键技术。文中介绍了具有完全自主知识产权的四通道可编程数字下变频器ASIC芯片的前端设计,包括芯片系统结构设计、各子模块设计（NCO／CIC滤波器／HB滤波器／FIR滤波器）,给出了基于VerilogHDI。语言设计的综合与仿真结果,以及基于SMIC0．18μm库的综合结果。     

GPS接收机镜像信号抑制

分析了GPS接收机镜像信号抑制的要求,设计应用于低中频GPS接收机的镜像抑制复数滤波器.滤波器基于OTA-C双二次结构,通过线性变换实现频率搬移.采用了带源极负反馈的全差分跨导器以扩大输入线性范围.设计了基于环形振荡器的数字调谐锁相环以减小滤波器频率偏差.电路采用0.18μm CMOS工艺实现.测试结果表明,滤波器带宽为3.1MHz,偏移5MHz抑制为50dB,频率修调误差小于±1.5%.镜像抑制大于35dB.1.8V电源电压下滤波器和修正电路电流分别为0.82mA和0.23mA.     

基于MAX2742型电路的GPS接收机设计

讨论MAX2742型GPS接收系统射频前端电路的特性及工作原理,介绍以其为基础的GPS接收机的设计,给出电路结构框图.     

Measuring Group Delay of Frequency Downconverter Devices Using a Chirped RF Modulated Signal

This paper discusses the implementation possibilities for making Group Delay measurements of RF frequency converting devices using a standard RF semiconductor Automatic Test Equipment (ATE) that cannot be done using the standard S-parameter measurement due to the difference in frequency from the input to the output of the device. We discuss how using a chirp waveform modulating an RF generator can be used to sweep the frequency response of a RF frequency-converting device and how to produce such a modulation waveform in digital signal processing. We will describe how to implement a group delay test based on our previous work in the baseband domain and how to understand the errors pertaining to measuring a Radio Frequency Receiver. The measurement of the Group Delay of an RF front-end filter and post down convert IF filter will be demonstrated. We will also describe how to produce and maintain a stable frequency reference so that any down converted signal would be a true representation of the modulation signal applied to the RF Source and not corrupted by Phase Noise. We will show how to implement a group delay test based on our previous work in the baseband domain and how to understand the errors pertaining to measuring a radio frequency receiver. The measurement of the group delay of an RF mixer and pre and post down convert RF/IF filters will be demonstrated. The central goal of this paper is to demonstrate how a group delay test can be done at RF, with a frequency translating device, in a cheap and effective manner on semiconductor Automatic Test Equipment in a production environment.     

基于PCM2902E的DRM接收前端设计

设计了基于软件无线电技术的DRM硬件接收前端,该设计可将RF前端接收到的模拟音频信号经过AD9220转换成数字信号送至FPGA,数字信号在FPGA中经过数字下变频和滤波抽取转化为48 kHz采样速率的中频信号,最后该信号封装成S/PDIF帧送至USB声卡芯片PCM2902E,通过USB接口传送给计算机,计算机装载的DRM接收软件进行DRM数字基带信号的软件解调,验证算法与电路设计的正确性.     

Combined Galileo/GPS architecture for enhanced sensitivity reception

Several new requirements and challenges are introduced with the transition of traditional navigation applications towards location-based services (LBSs). This paper introduces the HIGAPS receiver concept. Aim of the HIGAPS project is to develop the concept for a combined Galileo/GPS receiver that is specially tailored for LBSs, E-911, and other consumer market applications. After a brief overview of the receiver, the partitioning into analog hardware, digital hardware, and software is outlined. The architecture of the combined Galileo/GPS RF front-end is presented in low-IF topology. The digital baseband presents a highly parallel correlation architecture for combined Galileo/GPS reception, allowing fast times to fix for extended dwell times. Parallel digital signal processing combined with aiding data allows single-shot measurements particularly designed for LBSs. Differential correlation further improves the reception sensitivity. The coherently integrated predetection samples are thereby multiplied with the conjugated complex previous predetection samples.     

一种数字中频接收机的设计与实现

介绍了一种数字中频接收机的设计，对接收机的各个组成部分进行了原理分析和推导，包括可变带宽滤波器、ADC、基于多相滤波器的数字正交变换、抽取滤波器设计、基带信号处理单元设计，得出样机的各样性能参数。     

DVB-T接收前端下变频电路设计

介绍了DVB-T接收系统前端下变频的基本原理,设计了DVB-TRF信号到基带信号的下变频电路。电路基本原理为,调谐器将RF信号混频到中频,A/D转换器带通采样,将中频信号搬移到基带部分,得到数字基带信号。电路的控制部分由MCU和D/A转换器组成。本电路实现了对DVB-TRF信号的转换,得到了DVB-T数字基带信号。     

Design and Compliance Testing of a SiGe WCDMA Receiver IC With Integrated Analog Baseband

A 2.7-3.3 V 32-mA SiGe direct-conversion wide-band code division multiple access (WCDMA) receiver IC integrating the RF front-end and analog baseband on a single chip has been completed and measured. Analog performance specifications for the design were driven by the 3GPP specifications. To close the loop from 3GPP specifications to IC design specifications to hardware performance results, a subset of compliance tests for both the analog as well as the digital 3GPP specifications was performed. The IC design includes a bypassable low-noise amplifier (LNA), a quadrature direct-downconverter, an automatically tuned channel-select filter, wide dynamic-range baseband amplifiers, and a serial digital interface. Power-saving modes allow the LNA to be powered down when the input signal is sufficiently large, reducing current consumption to 23 mA. In addition, the entire Q-channel signal path can be optionally powered down during control-channel monitoring, further reducing current draw to 17 mA nominal. The IC showed full compliance with the static channel 3GPP specification tests performed, including all analog/RF compliance tests and a set of DPCH/spl I.bar/Ec/Ior sensitivity tests from 12.2 through 384 kb/s as measured with a software baseband processor.