RF LDMOS功率器件研制

基于ISE TCAD模拟软件对RF LDMOS器件的工艺流程和器件结构进行了优化设计,采用带栅极金属总线的版图结构降低栅电阻,同时简化了LDMOS器件的封装设计.通过实际流片和测试分析,重点讨论了漂移区注入剂量和漂移区长度对LDMOS器件的转移特性、击穿特性、截止频率及最大振荡频率的影响.测试结果表明该器件的阈值电压为1.8 V,击穿电压可达70 V,截止频率和最大振荡频率分别为9 GHz和12.6 GHz,并可提供0.7 W/mm的输出功率密度.     

L波段高功率密度LDMOS脉冲功率测试方法

报道了在工作电压50 V、频率1.2 GHz下,功率密度1.2 W/mm射频LDMOS功率器件的研制结果。由于大功率LDMOS功率器件输入阻抗小,在50Ω负载牵引系统下测试容易出现低频振荡,严重损坏待测器件。为了消除这种低频振荡,更好地进行功率测试,研究采用了直通-反射-传输线(TRL)低阻抗测试夹具。此种夹具可以很好地抑制低频率的功率增益,消除低频振荡;而且使阻抗调节器获得更多的低阻抗点,提高负载牵引系统测试的准确度。在低阻抗的负载牵引系统测试环境下,1.2 GHz下,脉冲输出功率在1 dB压缩点为109.4 W,功率密度达到1.2 W/mm。     

X波段大功率GaN HEMT的研制

在研制了AlGaN/GaN HEMT外延材料的基础上,采用标准工艺制作了2.5mm大栅宽AlGaN/GaNHEMT。直流测试中,Vg=0V时器件的最大饱和电流Ids可达2.4A,最大本征跨导Gmax为520mS,夹断电压Voff为-5V;通过采用带有绝缘层的材料结构及离子注入的隔离方式,减小了器件漏电,提高了击穿电压,栅源反向电压到-20V时,栅源漏电在10-6A数量级;单胞器件测试中,Vds=34V时,器件在8GHz下连续波输出功率为16W,功率增益为6.08dB,峰值功率附加效率为43.0%;2.5mm×4四胞器件,在8GHz下,连续波输出功率42W,功率增益8dB,峰值功率附加效率34%。     

高性能1mm AlGaN/GaN功率HEMTs研制

报道了基于蓝宝石衬底的高性能1mm AlGaN/GaN HEMTs功率器件.为了提高微波功率器件性能,采用新的欧姆接触和新型空气桥方案.测试表明,器件电流密度为0.784A/mm,跨导197mS/mm,击穿电压大于40V,截止态漏电较小,1mm栅宽器件的单位截止频率达到20GHz,最大振荡频率为28GHz,功率增益为11dB,功率密度为1.2W/mm,PAE为32%,两端口阻抗特性显示了在微波应用中的良好潜力.     

1 A/mm高电流密度金刚石微波功率器件

基于自对准栅电极制备技术,研制了具有低导通电阻和高电流密度的氢终端金刚石微波功率器件。采用高功函数金属Au与氢终端金刚石实现了良好的欧姆接触,接触电阻为0.73Ω·mm。得益于较低的源漏串联电阻和低损伤Al2O3栅介质原子层沉积工艺,金刚石微波器件的导通电阻低至4Ω·mm,饱和电流密度达1.01 A/mm,最大跨导为213 mS/mm,最大振荡频率达58 GHz。研究了该器件在2 GHz和10 GHz频率下连续波功率输出特性,发现在15 V低工作电压下即可分别实现1.56 W/mm和1.12 W/mm的输出功率密度,展现出自对准技术在研制高电流和高输出功率金刚石微波器件上的潜力。     

高性能1mm AlGaN/GaN功率HEMTs研制

报道了基于蓝宝石衬底的高性能1mm AlGaN/GaN HEMTs功率器件.为了提高微波功率器件性能，采用新的欧姆接触和新型空气桥方案．测试表明，器件电流密度为0.784A/mm，跨导197mS/mm，击穿电压大于40V，截止态漏电较小，1mm栅宽器件的单位截止频率达到20GHz，最大振荡频率为28GHz，功率增益为11dB，功率密度为1.2W/mm,PAE为32%,两端口阻抗特性显示了在微波应用中的良好潜力．     

n沟道4H-SiC MESFET研究

报告了4H-SiCMESFET的研制。通过对SiC关键工艺技术进行研究,设计出初步可行的工艺流程,并且制成单栅宽120μmn沟道4H-SiCMESFET,其主要直流特性为在Vds=30V时,最大漏电流密度Idss为56mA/mm,最大跨导Gm为15mS/mm;漏源击穿电压最高达150V;微波特性测试结果在fo=1GHz、Vds=32V时该器件最大输出功率7.05mW,在fo=1.8GHz、Vds=32V时最大输出功率3.1mW。     

蓝宝石衬底AlGaNöGaN 功率HEM Ts 研制

基于蓝宝石衬底的高微波特性 Al Ga N/Ga N HEMTs功率器件 ,器件采用了新的欧姆接触和新型空气桥方案。测试表明 ,器件电流密度 0 .784A/mm,跨导 1 97m S/mm,关态击穿电压 >80 V,截止态漏电很小 ,栅宽 1 mm的器件的单位截止频率 ( f T)达到 2 0 GHz,最大振荡频率 ( fmax) 2 8GHz,2 GHz脉冲测试下 ,栅宽 0 .75 mm器件 ,功率增益1 1 .8d B,输出功率 3 1 .2 d Bm,功率密度 1 .75 W/mm。     

利用改善的体连接技术制备SOI LDMOSFET

对功率器件中常用的体连接技术进行了改进,利用一次硼离子注入技术形成体连接.采用与常规1μm SOI(硅-绝缘体)CMOS工艺兼容的工艺流程,在SIMOX SOI片上制备了LDMOS结构的功率器件.器件的输出特性曲线在饱和区平滑,未呈现翘曲现象,说明形成的体连接有效地抑制了部分耗尽器件的浮体效应.当漂移区长度为2μm时,开态击穿电压达到10V,最大跨导17.5mS/mm.当漏偏压为5V时,SOI器件的泄漏电流数量级为1nA,而相应体硅结构器件的泄漏电流为1000nA.电学性能表明,这种改善的体连接技术能制备出高性能的SOI功率器件.     

磁控溅射AlN介质MIS栅结构的AlGaN/GaN HEMT

报道了一种X波段输出功率密度达10.4W/mm的SiC衬底AlGaN/GaN MIS-HEMT。器件研制中采用了MIS结构、凹槽栅以及场板,其中MIS结构中采用了磁控溅射的AlN介质作为绝缘层。采用MIS结构后,器件击穿电压由80V提高到了180V以上,保证了器件能够实现更高的工作电压。在8GHz、55V的工作电压下,研制的1mm栅宽AlGaN/GaN MIS-HEMT输出功率达到了10.4W,此时器件的功率增益和功率附加效率分别达到了6.56dB和39.2%。     

RF LDMOS功率器件关键参数仿真

在RF LDMOS功率器件中,击穿电压、截止频率fT和导通电阻Ron是器件的关键参数,为提高这几个器件性能参数可采取的各种措施又往往是相互矛盾和相互制约的。文中研究了几个参数之间的关系和优化方案。现在RF LDMOS功率器件在向高工作电压、高输出功率、高可靠性以及脉冲应用等方向发展。所研制器件采用沟背面源结构,采用场板技术降低栅漏电容,采用多晶硅金属硅化物结构降低栅阻。研制结果表明,在漏源工作电压6V、频率520MHz、连续波的测试条件下,输出功率达到5.6W,增益大于12dB,效率大于55%。     

Trenched‐Sinker LDMOSFET (TS‐LDMOS) Structure for 2 GHz Power Amplifiers

This paper proposes a new LDMOSFET structure with a trenched sinker for high‐power RF amplifiers. Using a low‐temperature, deep‐trench technology, we succeeded in drastically shrinking the sinker area to one‐third the size of the conventional diffusion‐type structure. The RF performance of the proposed device with a channel width of 5 mm showed a small signal gain of 16.5 dB and a maximum peak power of 32 dBm with a power‐added efficiency of 25% at 2 GHz. Furthermore, the trench sinker, which was applied to the guard ring to suppress coupling between inductors, showed an excellent blocking performance below ?40 dB at a frequency of up to 20 GHz. These results confirm that the proposed trenched sinker should be an effective technology both as a compact sinker for RF power devices and as a guard ring against coupling.     

1 W/mm RF power density at 3.2 GHz for a dual-layer RESURF LDMOStransistor

In this letter, we present state-of-the-art performance, in terms of output power density, for an RF-power LDMOS transistor. The novel device structure has a dual-layer RESURF of the drift region, which allows for a sub-μm channel length and a high breakdown voltage of 110 V. The output power density is more than 2 W/mm at 1 GHz and a V_DS=70 V, with a stable gain of 23 dB at V_DS=50 V. At 3.2 GHz the power density is over 1 W/mm at V_DS=50 V and 0.6 W/mm at V_DS=28 V. These results are to our knowledge the best ever for silicon power MOSFETs     

具有漂移区场氧化层结构的射频LDMOS器件研究

介绍了一种改进型RF LDMOS器件。通过对传统RF LDMOS器件的工艺流程进行修改,并在漂移区上方引入场氧化层结构,改善了器件的准饱和现象。当工作在Vgs=5 V,Vds=10 V条件下时,与传统RF LDMOS器件相比,改进后RF LDMOS器件的跨导提高约81%,截止频率提高约89%,击穿电压提高约15%。     

DC and RF characteristics of E-mode Ga/sub 0.51/In/sub 0.49/P-In/sub 0.15/Ga/sub 0.85/As pseudomorphic HEMTs

The DC and RF characteristics of Ga/sub 0.49/In/sub 0.51/P-In/sub 0.15/Ga/sub 0.85/As enhancement- mode pseudomorphic HEMTs (pHEMTs) are reported for the first time. The transistor has a gate length of 0.8 /spl mu/m and a gate width of 200 /spl mu/m. It is found that the device can be operated with gate voltage up to 1.6 V, which corresponds to a high drain-source current (I/sub DS/) of 340 mA/mm when the drain-source voltage (V/sub DS/) is 4.0 V. The measured maximum transconductance, current gain cut-off frequency, and maximum oscillation frequency are 255.2 mS/mm, 20.6 GHz, and 40 GHz, respectively. When this device is operated at 1.9 GHz under class-AB bias condition, a 14.7-dBm (148.6 mW/mm) saturated power with a power-added efficiency of 50% is achieved when the drain voltage is 3.5 V. The measured F/sub min/ is 0.74 dB under I/sub DS/=15 mA and V/sub DS/=2 V.     

A Short-Channel SOI RF Power LDMOS Technology With$hboxTiSi_2$Salicide on Dual Sidewalls With Cutoff Frequency$f_T sim hbox19.3 hboxGHz$

In this letter, a CMOS-compatible silicon-on-insulator (SOI) RF laterally diffused MOS (LDMOS) technology is proposed based on TiSi₂ salicide with SiO₂/Si₃N₄ dual sidewalls. The use of dual sidewalls yields a large process margin for defining drift regions and preventing source-gate silicide bridging. This technology improves the cutoff frequencies and the maximum oscillation frequencies by 27%-42% and 14%-22%, respectively, for a gate length in the range of 0.5-0.25 mum. For the shortest 0.25-mum gate length, a record cutoff frequency of 19.3 GHz and a high breakdown voltage of 16.3 V are achieved simultaneously for SOI RF LDMOS. This LDMOS technology is suitable for 3.6-V-supply 0-3-GHz power RFIC applications     

Influence of interface state charges on RF performance of LDMOS transistor

Si-LDMOS transistor is studied by TCAD simulation for improved RF performance. In LDMOS structure, a low-doped reduced surface field (RESURF) region is used to obtain high breakdown voltage, but it reduces the transistor RF performance due to high on-resistance. The interface charges between oxide and the RESURF region are studied and found to have a strong impact on the transistor performance both in DC and RF. The presence of excess interface state charges at the RESURF region results not only higher DC drain current but also improved RF performance in terms of power, gain and efficiency. The most important achievement is the enhancement of operating frequency and RF output power is obtained well above 1 W/mm up to 4 GHz.     

30 nm T-gate enhancement-mode InAlN/AlN/GaN HEMT on SiC substratesfor future high power RF applications

The DC and RF performance of 30 nm gate length enhancement mode (E-mode) InAlN/AlN/GaN high electron mobility transistor (HEMT) on SiC substrate with heavily doped source and drain region have been investigated using the Synopsys TCAD tool. The proposed device has the features of a recessed T-gate structure, InGaN back barrier and Al₂O₃ passivated device surface. The proposed HEMT exhibits a maximum drain current density of 2.1 A/mm, transconductance g_m of 1050 mS/mm, current gain cut-off frequency f_t of 350 GHz and power gain cut-off frequency f_max of 340 GHz. At room temperature the measured carrier mobility (μ), sheet charge carrier density (n_s) and breakdown voltage are 1580 cm²/(V·s), 1.9×10¹³ cm^-2, and 10.7 V respectively. The superlatives of the proposed HEMTs are bewitching competitor or future sub-millimeter wave high power RF VLSI circuit applications.