基于正交试验设计的塑封球栅阵列器件焊点工艺参数与可靠性关系研究

基于正交试验设计法对塑封球栅阵列(PBGA)器件焊点工艺参数与可靠性关系进行了研究.采用混合水平正交表L₁₈(2×3⁷)设计了18种不同工艺参数组合的PBGA测试样件,进行了546小时、最大循环周数2140周的PBGA测试样件可靠性加速热循环试验.基于试验结果进行了极差分析和方差分析;研究了PBGA测试样件寿命的威布尔分布;采用有限元分析方法对热循环加载条件下PBGA焊点内应力应变分布进行了研究.试验结果表明失效焊点裂纹出现于焊点与芯片基板的交界面上.研究结果表明:样件规格对PBGA焊点可靠性有高度显著影响,芯片配重对PBGA焊点可靠性有显著的影响,焊盘直径和钢网厚度对PBGA焊点可靠性无显著影响;最优工艺参数组合为:S2D2G2M1和S2D2G2M2.有限元分析表明在热循环加载条件下PBGA器件内应力最大区域位于焊点与芯片基板的接触面上,裂纹首先在焊点与芯片基板的接触面处产生,有限元分析结果与试验结果相吻合.     

温度载荷下光互连模块对准偏移分析

建立了板级光互连模块有限元分析模型,对其进行温度载荷下的有限元分析,分别获取了垂直腔面发射激光器（VCSEL,vertical cavity surface emitting laser）与耦合元件、耦合元件与光波导两个关键位置处在不同温度时刻的轴向、水平和垂直方向的对准偏移。结果表明：光互连模块关键位置的部件在温度载荷下会产生轴向、水平和垂直方向的对准偏移;在一个温度载荷周期内位置偏移值随着温度变化而变化,其中在低温保温阶段对准偏移值最大,在高温保温阶段对准偏移最小;在低温阶段关键位置处的轴向位置偏移最大,并且12路光通道中水平位置偏移呈现两端偏移大,中间偏移小的趋势。     

基于正交法的FBGA焊点可靠性优化研究

在芯片紧密度、功耗都在增加的微电子封装领域,FBGA封装在同体积下有较大的存储容量。基于有限元和正交法,进行了FBGA焊点热循环载荷下的可靠性分析,并进行了更稳健的焊点结构参数优化设计。结果表明,焊点阵列对FBGA结构热可靠性有重要影响;优化方案组合为12×12焊点阵列,焊点径向尺寸为0.42 mm,焊点高度为0.38 mm,焊点间距为0.6 mm。经过优化验证,该优化方案的等效塑性应变范围较原始设计方案降低了89.92%,信噪比提高到17.72 dB,实现了焊点参数优化目标。     

热循环参数及基板尺寸对焊点可靠性的影响

采用Ansys软件建立BGA倒装芯片模型考察焊点的热应力。通过改变热循环保温时间、温度范围和最高温度,研究各参数对焊点热疲劳寿命的影响,同时也考察了基板的长度和厚度的影响。采用Coffin-Manson方程计算并比较热循环寿命。结果表明:随着热循环高低温停留时间、温度范围以及最高热循环温度的增大,热循环寿命减小,最小寿命为879周;同时热循环寿命也随着基板长度和厚度的增大而减小。     

基于扭转载荷的微尺度CSP焊点应力应变分析与优化

建立了微尺度芯片尺寸封装焊点有限元分析模型并对其进行扭转应力应变仿真分析与实验验证.分析了焊点材料、焊点直径、焊盘直径和焊点高度对焊点扭转应力应变的影响;以焊点材料、焊点直径、焊盘直径和焊点高度为设计变量,采用响应面法设计了29组不同水平组合的焊点模型并获取了相应焊点扭转应力,建立了焊点扭转应力与焊点结构参数的回归方程,结合遗传算法对焊点结构参数进行了优化.结果表明：焊点材料为SAC305时扭转应力应变最大,焊点最大扭转应力应变随焊点直径和焊盘直径增加而减小、随焊点高度增大而增大;最优焊点结构参数水平组合为：焊点材料SAC305、焊点直径0.22mm、焊盘直径0.14mm和焊点高度0.14mm;仿真验证表明最优焊点最大扭转应力下降了3.7MPa.     

不同基板的CBGA焊点在热循环下的力学特性研究

采用粘塑性本构Anand方程描述SnPb钎料的变形行为,用有限元方法对CBGA组件焊点结构进行二维模型分析;同时,选用不同的基板材料(Al2O3、AlN、SiC),考察焊点在热循环加载过程中的应力应变等力学行为.研究结果表明,最外侧焊点受到的应力应变最大,所以裂纹最有可能从最外侧焊点处萌生,并沿着基板一侧扩展;焊点的高应力发生在热循环的低温阶段,升降温过程中的蠕变和非弹性应变的累积显著,应力应变迟滞环在热循环的最初几个周期内就能很快稳定.模拟结果得出,采用BeO基板材料时焊点的应力应变最小,其可靠性最高.     

基于回归分析和遗传算法的BGA焊点功率载荷热应力分析与优化

建立了球栅阵列BGA（Ball Grid Array）焊点有限元分析模型,选取焊点高度、焊点最大径向尺寸、上焊盘直径和下焊盘直径作为设计变量,以焊点应力作为目标值,采用响应曲面法设计了29组不同水平组合的焊点模型并建模进行仿真计算,建立了焊点应力与结构参数的回归方程,基于回归方程结合遗传算法对焊点结构参数进行了优化,获得了焊点应力最小的结构参数最优水平组合.结果表明：对于无铅焊料SAC387,焊点应力随焊点的高度增加而减小,随最大径向尺寸的减小而减小;应力最小的焊点水平组合为：焊点高度0.38mm、最大径向尺寸0.42mm、上焊盘直径0.34mm和下焊盘直径0.35mm;对最优水平组合仿真验证表明优化后焊点最大应力下降了4.66MPa,实现了BGA焊点的结构优化.     

PBGA无铅焊点热可靠性优化研究

在田口实验法的基础上,采用非线性有限元建模,对温度循环载荷作用下的PBGA无铅焊点进行可靠性优化研究。L18(21×37)田口正交表被选用来分析PBGA封装体的8个控制因子,包括PCB的尺寸和厚度、基板的尺寸和厚度、焊点的直径和高度、芯片以及塑封的厚度。通过田口实验法,得出了关于PBGA最佳的结构参数组合,其中最重要的控制因子为基板厚度和焊点高度,最佳参数分别为0.66mm和0.60mm。     

气孔缺陷对同轴电缆焊点热疲劳寿命影响

利用ANSYS软件建立了热循环条件下同轴电缆焊点的三维有限元模型,分析了气孔的大小及位置对焊点在热循环过程中的应力应变分布特征的影响,结合Manson-Coffin方程预测了不同气孔大小及位置对焊点的热疲劳寿命的影响.结果表明:气孔的存在使焊点的热疲劳寿命急剧缩短;相同尺寸的气孔存在于焊点内部时位置的改变对热疲劳寿命影响很小;处于焊点内部的气孔对焊点的疲劳寿命影响要小于靠近表面的气孔;处于焊点根部的气孔对焊点疲劳寿命的影响要远大于其它位置的气孔;气孔越大,对焊点的疲劳寿命影响越大.     

基于随机振动过程应力分析的BGA焊点结构优化

建立了板级BGA(Ball Grid Array)焊点有限元分析模型，选取芯片高度、焊点直径、焊点高度、焊点间距作为设计变量，以焊点应力作为响应目标，分别采用田口正交及曲面响应法设计了25组不同水平组合的焊点模型并进行仿真计算，通过数理统计分析及回归分析对焊点结构参数进行了优化，获得了焊点应力最小结构参数最优水平组合.结果表明：在相同条件下，曲面响应优化的结果优于田口正交的结果；应力最小的焊点水平组合为焊点直径0.32 mm，焊点高度0.20 mm，焊点间距0.36 mm；最优水平组合等效应力值为0.3915 MPa，降低了0.65 MPa，实现了BGA焊点结构参数的优化.     

光纤固定软钎焊焊点的三维形态模拟

本文在建立光纤固定软钎焊焊点模型及能量边界条件的基础上,利用有限元方法对焊点三维形态进行数值模拟并分析材料及结构等参数对焊点形态的影响规律.基于能量最小原理并利用形态模拟数据,得出钎料量及焊盘尺寸对光纤与焊盘间隙高度的影响规律,以及光纤横向偏移量对回复力的影响规律.研究结果表明:针对一定的焊盘相对尺寸,当钎料量大于临界值,最小间隙高度随着钎料量的增加而成线性增加;光纤横向偏移量小于一定值时,回复力随着偏移量的增加成线性增加.研究结果对于通过调整结构及工艺参数来控制光纤对准偏移具有指导意义.     

SMT焊点元件与基板间隙的预测及其对焊点三维形态的影响

基于能量最小原理，采用三维有限元方法，考究了片式元件与基板的间隙对ＳＭＴ焊点三维开矿的影响，利用焊点系统的能量数据，分析元件与基板的间隙。研究表明，元件与基板的间隙对焊点三维形态有重要影响，元件与基板的间隙随焊点钎料量的增加和焊盘伸出长度匠减小而增加，提出了间隙与钎料量，焊盘伸出长度关系的回归模型。     

片式元件与基板间隙对无铅焊点可靠性的影响

采用非线性有限元方法,讨论了片式元件与基板的间隙对Sn-2.5Ag-0.7Cu无铅钎料焊点的应力分布和热疲劳寿命的影响。结果表明,当间隙高度为0.1~0.2mm时,焊点薄弱处——元件底部拐角处、焊根的顶部和底部以及焊趾顶部具有较低的应力,此时预测得到焊点的热疲劳寿命也最长。这一结果对于焊点几何形态的设计及优化具有指导意义。     

Effect of substrate flexibility on solder joint reliability. Part II: finite element modeling

Solder joint fatigue failure is a serious reliability concern in area array technologies, such as flip chip and ball grid array packages of integrated-circuit chips. The selection of different substrate materials could affect solder joint thermal fatigue life significantly. The mechanism of substrate flexibility on improving solder joint thermal fatigue was investigated by thermal mechanical analysis (TMA) technique and finite element modeling. The reliability of solder joints in real flip chip assembly with both rigid and compliant substrates was evaluated by accelerated temperature cycling test. Finite element simulations were conducted to study the reliability of solder joints in flip chip on flex assembly (FCOF) and flip chip on rigid board assembly (FCOB) applying Anand model. Based on the finite element analysis results, the fatigue lives of solder joints were obtained by Darveaux’s crack initiation and growth model. The thermal strain/stress in solder joints of flip chip assemblies with different substrates were compared. The results of finite element analysis showed a good agreement with the experimental results. It was found that the thermal fatigue lifetime of FCOF solder joints was much longer than that of FCOB solder joints. The thermal strain/stress in solder joints could be reduced by flex buckling or bending and flex substrates could dissipate energy that otherwise would be absorbed by solder joints. It was concluded that substrate flexibility has a great effect on solder joint reliability and the reliability improvement was attributed to flex buckling or bending during temperature cycling.     

Stacked solder bumping technology for improved solder joint reliability

Solder joint failure is a serious reliability concern in flip-chip and ball grid array packages of integrated-circuit chips. In current industrial practice, the solder joints take on the shape of a spherical segment. Mathematical calculations and finite element modeling have shown that hourglass-shaped solder joints would have the lowest plastic strain and stress during a temperature cycle, thus the longest lifetime. In an effort to improve solder joint reliability, we have developed a stacked solder bumping technique for fabricating triple-stacked hourglass-shaped solder joints. This solder bumping technology can easily control the solder joint shape and height. The structure of triple-stacked solder joints consists of an inner cap, middle ball and outer cap. The triple-stacked solder joints are expected to have greater compliance than conventional solder joints and are able to relax the stresses caused by the coefficient of thermal expansion mismatching between the silicon chips and substrates since it has a greater height. Furthermore, the hourglass-shaped solder joints are to have a much lower stress/strain concentration at the interface between the solder joint and the silicon die as well as at the interface between the solder joint and substrate than barrel-shaped solder joints, especially around the corners of the interfaces. In this paper, the solder bumping process is designed and joint reliability is evaluated. Mechanical tests have been carried out to characterize the adhesion strength of the solder joints. The interfaces of the solder joints are investigated by scanning electron microscopy and energy dispersive X-ray analysis. Temperature cycling results show that the triple-stacked hourglass-shaped solder joints are more reliable than the traditional spherical-shaped solder joints.     

Quantitative characterization of 96.5Sn3.5Ag and 80Au20Sn opticalfiber solder bond joints on silicon micro-optical bench substrates

Stress analysis of optical fiber solder bond joints on silicon micro-optical bench substrates under thermal cycle loading was investigated using two-dimensional (2-D) and three-dimensional (3-D) finite element analyses. Finite element simulations were carried out to investigate the effect of the distance between the fiber and the silicon substrate for planar and v-groove solder attachment geometries. It was found that the maximum stress-strain along the interface of the solder and silicon substrate increases as the distance between the fiber and substrate decreases for both geometries. The solder bond strength under thermal loading was also examined to determine the influence of alternative solder material. Favorable results were obtained for 96.5Sn3.5Ag solder as compared to 80Au20Sn solder. If adequate space is provided between the fiber and silicon v-groove inclined walls, the reliability of the v-groove geometry is projected to be comparable to an optimally designed planar bond joint geometry     

片式元件与基板间隙对SnAgCu系无铅焊点的应力分析

文章采用非线性有限元方法,重点讨论了片式元件与基板的间隙对Sn-2.5Ag-0.7Cu无铅钎料焊点的应力应变分析。研究表明,在实际中适当增大间隙高度有利于改善焊点的应力分布情况。当间隙高度为0.1mm~0.2mm时,元件底部拐角处、焊根的顶部和底部以及焊趾顶部的应力值普遍较低,应力分布得到了较好的改善,这一结果对于焊点的优化及设计具有指导意义。     

PBGA封装热可靠性分析

对PBGA封装体建立了有限元数值模拟分析模型。模型采用无铅焊点,完全焊点阵列形式。研究了封装体在经历IPC9701标准下的五种不同温度循环加载后,受到的热应力、应变,以及可能的失效形式。结果表明,焊点是封装体结构失效的关键环节,焊点所受应力大小与焊点位置有关。比较了不同温度循环下封装体的疲劳寿命。其结果为提高封装体的可靠性和优化设计提供了理论依据。