一种热感集成电路功耗模型及其对动态电压调整技术的影响

提出了一种新型热感功耗模型,该模型能够准确估计出电压调整情况下的功耗和温度.实验结果表明如果忽略热效应,泄漏功耗将会被低估最高达52%.使用电压调整技术对电路的能量消耗和温度进行协同优化时,两者具有不一致的优化方向.温度是未来集成电路发展的一个重要限制因素,而温度优化方法可以降低电路温度最高达12℃,同时其能耗的增长低于最优解的1.8%.     

一款高精度低功耗电压基准的设计与实现

设计了一款高输出电压情况下的高精度低功耗电压基准电路.电路采用了比例采样负反馈结构达到较高和可控的输出电压,并利用曲率补偿电路极大地减小了输出电压的温度系数.针对较宽输入电压范围内的超低线性调整率规格,给出了多级带隙级联的电路结构.针对功耗和超低负载调整率的问题,电路采用了基于运算放大器的限流模式和内置大尺寸横向扩散金属氧化物半导体(LDMOS)晶体管的设计.该电路在CSMC 0.25 μm高压BCD工艺条件下进行设计、仿真和流片,测试结果表明,该电压基准输出电压为3.3V,温度系数为19.4×10-6/℃,线性调整率为5.6 μV/V,负载调整率为23.3 μV/V,工作电流为45 μA.     

改进结构的低压低功耗CMOS带隙基准源

提出了一种低电压、低功耗、中等精度的带隙基准源,针对电阻分流结构带隙基准源在低电源电压下应用的不足作出了一定的改进,整体电路结构简单且便于调整,同时尽可能地减少了功耗.该电路采用UMC 0.18 μm Mixed Mode 1.8 V CMOS工艺实现.测试结果表明,电路在1 V电源电压下,在-20～30℃的温度范围内,基准电压的温度系数为20×10-6/℃,低频时的电源电压抑制比为-54 dB,1 V电源电压下电路总功耗仅为3μW.     

单相AC-DC变换电路设计及试验

该单相AC-DC变换电路以有源功率因数控制器UCC28019为核心,STM32F103做主控芯片,采用主控芯片片上DAC调节UCC28019电压误差放大器反馈端,控制输出电压稳定输出;设计功率因数测量电路、输出保护电路、功率因数调整电路等电路模块。经测试,系统输入电压为24 V时,输出2 A电流时可稳定输出36 V电压,负载调整率为0.02%,电压调整率为0.028%,功率因数测量最大误差为0.02,过流保护动作电流为2.54 A,交流输入侧功率因数校正后最高达99.9%,转换效率达96.7%,功率因数在0.8¹.0稳定可调。     

深亚微米功耗优化的简化模型

结合DVS和ABB技术,同时调整工作电压Vdd和衬底偏置电压Vbs的方法能有效降低深亚微米功耗.在解析方法的基础上提出了已知频率下功耗优化的Vdd,Vbs简化模型.模型中任意频率下对应的优化Vdd,Vbs值中之一为常数,避免了解析方法中的超越方程求解.文章进一步对不同电容时简化模型中的参数提出了近似估计方法SEM.0.18μm和0.07μm工艺参数下模拟试验表明,采用简化模型以及SEM估计方法得到的优化功耗值与解析方法得到的结果十分接近,最大误差为2%和5%,平均误差为0.8%和1%.模拟实验表明本文的模型及方法在保证优化精度的基础上减小了计算复杂度,适用于深亚微米下的功耗优化及评估.     

一种适用于Buck型DC/DC变换器的高精度片上电流采样电路

电流采样电路作为电流控制的DC/DC变换器重要组成部件之一,其精度和响应速度已受到越来越高的重视.提出的电流采样电路没有使用运算放大器,简化了电路结构,降低了功耗.同时,电路中引入的补偿电流进一步提高了采样的精度.基于0.5μm CMOS工艺实现该电路,HSPICE模拟仿真结果表明该电路具有较高的采样精度,最高可达99.9%,且在负载、输入电压、温度变化时,采样精度波动很小.     

基于运动估计算法的PE模块的低功耗设计

基于运动估计算法的PE模块的硬件结构设计,文中提出了集群式电压调节算法,给电路分配双电压供电,相较于使用单一电压的电路,功耗减少了45.3%.在此基础上,进一步采用门控时钟技术来对电路精细化管理,取得了63.2%的功耗节省.此外,针对多电压电路结构,提出了一种新的电平转化器以获得更小的功耗和延时.     

VSF:CMOS组合电路的静态功耗评估模型

为了解决利用晶体管级电路模拟分析CMOS电路静态功耗时模拟时间随电路规模增大迅速增加的问题,在分析晶体管堆叠效应对标准单元泄漏电流影响的基础上,定义了归一化堆叠系数和电路等效堆叠系数的概念,提出了基于电路有效堆叠系数的静态功耗评估模型.该模型可用于CMOS组合电路静态功耗估算和优化.实验结果表明使用该模型进行静态功耗估算时,不需要进行Hspice模拟.针对ISCAS85基准电路的静态功耗优化结果表明,利用该模型能够取得令人满意的静态功耗优化效果,优化速度大大提高.     

VSF:CMOS组合电路的静态功耗评估模型

为了解决利用晶体管级电路模拟分析CMOS电路静态功耗时模拟时间随电路规模增大迅速增加的问题,在分析晶体管堆叠效应对标准单元泄漏电流影响的基础上,定义了归一化堆叠系数和电路等效堆叠系数的概念,提出了基于电路有效堆叠系数的静态功耗评估模型.该模型可用于CMOS组合电路静态功耗估算和优化.实验结果表明使用该模型进行静态功耗估算时,不需要进行Hspice模拟.针对ISCAS85基准电路的静态功耗优化结果表明,利用该模型能够取得令人满意的静态功耗优化效果,优化速度大大提高.     

一种降低电路泄漏功耗的多阈值电压方法

目前,多阈值电压方法是缓解电路泄漏功耗的有效手段之一。但是,该方法会加重负偏置温度不稳定性(NBTI)效应,导致老化效应加剧,引起时序违规。通过找到电路的潜在关键路径集合,运用协同优化算法,将关键路径集合上的门替换为低阈值电压类型,实现了一种考虑功耗约束的多阈值电压方法。基于45 nm工艺模型及ISCAS85基准电路的仿真结果表明,在一定功耗约束下,该方法的时延改善率最高可达12.97%,明显优于常规多阈值电压方法。电路的规模越大,抗泄漏功耗的效果越好。     

New Thermal‐Aware Voltage Island Formation for 3D Many‐Core Processors

The power consumption of 3D many‐core processors can be reduced, and the power delivery of such processors can be improved by introducing voltage island (VI) design using on‐chip voltage regulators. With the dramatic growth in the number of cores that are integrated in a processor, however, it is infeasible to adopt per‐core VI design. We propose a 3D many‐core processor architecture that consists of multiple voltage clusters, where each has a set of cores that share an on‐chip voltage regulator. Based on the architecture, the steady state temperature is analyzed so that the thermal characteristic of each voltage cluster is known. In the voltage scaling and task scheduling stages, the thermal characteristics and communication between cores is considered. The consideration of the thermal characteristics enables the proposed VI formation to reduce the total energy consumption, peak temperature, and temperature gradients in 3D many‐core processors.     

A Design-Specific and Thermally-Aware Methodology for Trading-Off Power and Performance in Leakage-Dominant CMOS Technologies

As CMOS technology scales deeper into the nanometer regime, factors such as leakage power and chip temperature emerge as critically important concerns for high-performance VLSI design. Consequently, enhancing processing performance is no longer the most important factor that dominates future circuit design considerations. This paper, for the first time, proposes a systematic methodology to determine a generalized design optimization metric for simultaneously trading-off power and performance in nanometer scale integrated circuits to achieve design-specific targets. The methodology incorporates interconnect effects as well as electrothermal couplings between substrate temperature, power, and performance for nanometer scale design optimization. Implications of choosing a specific design optimization metric on power, performance, and operating temperature are illustrated and discussed. The proposed methodology is shown to provide a more meaningful optimization metric (for power-performance tradeoff analysis) and basis, with considerations of chip-level thermal management including maximum allowable operating temperature and packaging/cooling solutions. Furthermore, implications of CMOS technology scaling and parameter variations on the proposed methodology are discussed.      

Temperature-adaptive voltage tuning for enhanced energy efficiency in ultra-low-voltage circuits

Circuits optimized for minimum energy consumption operate typically in the subthreshold regime with ultra-low power-supply voltages. Speed of a subthreshold logic circuit is enhanced with an increase in the die temperature. The excessive timing slack observed in the clock period of subthreshold logic circuits at elevated temperatures provides opportunities to lower the active-mode energy consumption. A temperature-adaptive dynamic-supply voltage-tuning technique is proposed in this paper to reduce the high-temperature energy consumption without degrading the clock frequency in ultra-low-voltage subthreshold logic circuits. Results indicate that the energy consumption can be lowered by up to 40% by dynamically scaling the supply voltage at elevated temperatures. An alternative technique based on temperature-adaptive reverse body bias to exponentially reduce the subthreshold leakage currents at elevated temperatures is also investigated. The active-mode energy consumption with two temperature-adaptive voltage-tuning techniques is compared. The impact of the process parameter and supply voltage variations on the proposed temperature-adaptive voltage scaling techniques is evaluated.     

Reversed Temperature-Dependent Propagation Delay Characteristics in Nanometer CMOS Circuits

The supply voltage to threshold voltage ratio is reduced with each new technology generation. The gate overdrive variation with temperature plays an increasingly important role in determining the speed characteristics of CMOS integrated circuits. The temperature-dependent propagation delay characteristics, as shown in this brief, will experience a complete reversal in the near future. Contrary to the older technology generations, the speed of circuits in a 45-nm CMOS technology is enhanced when the temperature is increased at the nominal supply voltage. Operating an integrated circuit at the prescribed nominal supply voltage is not preferable for reliable operation under temperature fluctuations. A design methodology based on optimizing the supply voltage for temperature-variation-insensitive circuit performance is proposed in this brief. The optimum supply voltage is 45% to 53% lower than the nominal supply voltage in a 180-nm CMOS technology. Alternatively, the optimum supply voltage is 15% to 35% higher than the nominal supply voltage in a 45-nm CMOS technology. The speed and energy tradeoffs in the supply voltage optimization technique are also presented     

Scaling trends of on-chip power distribution noise

The design of power distribution networks in high-performance integrated circuits has become significantly more challenging with recent advances in process technologies. As on-chip currents exceed tens of amperes and circuit clock periods are reduced well below a nanosecond, the signal integrity of on-chip power supply has become a primary concern in the integrated circuit design. The scaling behavior of the inductive and resistance voltage drops across the on-chip power distribution networks is the subject of this paper. The existing work on power distribution noise scaling is reviewed and extended to include the scaling behavior of the inductance of the on-chip global power distribution networks in high-performance flip-chip packaged integrated circuits. As the dimensions of the on-chip devices are scaled by S, where S>1, the resistive voltage drop across the power grids remains constant and the inductive voltage drop increases by S, if the metal thickness is maintained constant. Consequently, the signal-to-noise ratio decreases by S in the case of resistive noise and by S/sup 2/ in the case of inductive noise. As compared to the constant metal thickness scenario, ideal interconnect scaling of the global power grid mitigates the unfavorable scaling of the inductive noise but exacerbates the scaling of resistive noise by a factor of S. On-chip inductive noise will, therefore, become of greater significance with technology scaling. Careful tradeoffs between the resistance and inductance of the power distribution networks will be necessary in nanometer technologies to achieve minimum power supply noise.     

A high precision high PSRR bandgap reference with thermal hysteresis protection

To meet the accuracy requirement for the bandgap voltage reference by the increasing data conversion precision of integrated circuits,a high-order curvature-compensated bandgap voltage reference is presented employing the characteristic of bipolar transistor current gain exponentially changing with temperature variations.In addition,an over-temperature protection circuit with a thermal hysteresis function to prevent thermal oscillation is proposed.Based on the CSMC 0.5μm 20 V BCD process,the designed cir...     

Temperature-adaptive voltage scaling for enhanced energy efficiency in subthreshold memory arrays

Static random access memory (SRAM) circuits optimized for minimum energy consumption typically operate in the subthreshold regime with ultra low-power-supply voltages. Both the read and the write propagation delays of a subthreshold memory circuit are significantly reduced with an increase in the die temperature. The excessive timing slack observed in the clock period of constant-frequency subthreshold memory circuits at elevated temperatures provides new opportunities to lower the active-mode energy consumption. Temperature-adaptive dynamic supply voltage tuning (TA-DVS) technique is proposed in this paper to reduce the high-temperature energy consumption of ultra low-voltage subthreshold SRAM arrays. Results indicate that the energy consumption can be lowered by up to 32.8% by dynamically scaling the supply voltage at elevated temperatures. The impact of the temperature-adaptive dynamic supply voltage scaling technique on the data stability of the subthreshold SRAM bit-cells is presented. The effectiveness of the TA-DVS technique under process parameter and supply voltage variations is evaluated. An alternative technique based on temperature-adaptive reverse body bias (TA-RBB) to exponentially reduce the subthreshold leakage currents at elevated temperatures is also investigated. The active-mode energy consumption characteristics of the two temperature-adaptive voltage tuning techniques are compared.     

Analysis and optimization of nanometer CMOS circuits for soft-error tolerance

Nanometer circuits are becoming increasingly susceptible to soft errors due to alpha-particle and atmospheric neutron strikes as device scaling reduces node capacitances and supply/threshold voltage scaling reduces noise margins. It is becoming crucial to add soft-error tolerance estimation and optimization to the design flow to handle the increasing susceptibility. The first part of this paper presents a tool for accurate soft-error tolerance analysis of nanometer circuits (ASERTA) that can be used to estimate the soft-error tolerance of nanometer combinational circuits. The tolerance estimates generated by the tool match SPICE-generated estimates closely while taking orders of magnitude less computation time. The second part of the paper presents a tool for soft-error tolerance optimization of nanometer circuits (SERTOPT), which uses the tolerance estimates generated by ASERTA. The number of errors propagated to the primary outputs (POs) is minimized by adding optimal amounts of capacitive loading to the POs of the logic circuit. Using a novel delay-assignment-variation-based optimization methodology, the sizes, supply voltages, and threshold voltages of internal gates (not primary outputs) are chosen to minimize the energy and delay overhead due to the added capacitive loads. Experiments on ISCAS'85 benchmarks show that 79.3% soft-error reduction can be obtained on the average with modest increase in circuit delay and energy. Comparison with other techniques shows that our approach has a significantly better energy-delay-reliability tradeoff compared with others.     

Exploring the design space of mixed swing quadrail for low-powerdigital circuits

This paper describes and explores the design space of a mixed voltage swing methodology for lowering the energy per switching operation of digital circuits in standard submicron complementary metal-oxide-semiconductor (CMOS) fabrication processes. Employing mixed voltage swings expands the degrees of freedom available in the power-delay optimization space of static CMOS circuits. In order to study this design space and evaluate the power-delay tradeoffs, analytical polynomial formulations for power and delay of mixed swing circuits are derived and HSPICE simulation results are presented to demonstrate their accuracy. Efficient voltage scaling and transistor sizing techniques based on our analytical formulations are proposed for optimizing energy/operation subject to target delay constraints; up to 2.2× improvement in energy/operation is demonstrated for an ISCAS'85 benchmark circuit using these techniques. Experimental results from HSPICE simulations and measurements from an And-Or-Invert (AO1222) test chip fabricated in the Hewlett-Packard 0.5 μm process are presented to demonstrate up to 2,92× energy/operation savings for optimized mixed swing circuits compared to static CMOS     

Minimizing power consumption in digital CMOS circuits

An approach is presented for minimizing power consumption for digital systems implemented in CMOS which involves optimization at all levels of the design. This optimization includes the technology used to implement the digital circuits, the circuit style and topology, the architecture for implementing the circuits and at the highest level the algorithms that are being implemented. The most important technology consideration is the threshold voltage and its control which allows the reduction of supply voltage without significant impact on logic speed. Even further supply reductions can be made by the use of an architecture-based voltage scaling strategy, which uses parallelism and pipelining, to tradeoff silicon area and power reduction. Since energy is only consumed when capacitance is being switched power can be reduced by minimizing this capacitance through operation reduction choice of number representation, exploitation of signal correlations, resynchronization to minimize glitching, logic design, circuit design, and physical design. The low-power techniques that are presented have been applied to the design of a chipset for a portable multimedia terminal that supports pen input, speech I/O and full-motion video. The entire chipset that performs protocol conversion, synchronization, error correction, packetization, buffering, video decompression and D/A conversion operates from a 1.1 V supply and consumes less than 5 mW