部分耗尽SOI MOSFETs中沟道的非对称掺杂效应

利用二维模拟软件对部分耗尽SoI器件中的非对称掺杂沟道效应进行了模拟.详细地研究了该结构器件的电学性能,如输出特性,击穿特性.通过本文模拟发现部分耗尽SOI非对称掺杂沟道相比传统的部分耗尽SOI,能抑制浮体效应,改善器件的击穿特性.同时跟已有的全耗尽SOI非对称掺杂器件相比,部分耗尽器件性能随参数变化,在工业应用上具有可预见性和可操作性.因为全耗尽器件具有非常薄的硅膜,而这将引起如前栅极跟背栅极的耦合效应和热电子退化等寄生效应.     

0.15μm薄膜全耗尽MOS／SOI器件的设计和研制

利用自己开发的二维数值深亚微米SOI器件模拟软件,较为详细地分析了沟道长度小于o.2μm的 SOI器件的阈值电压特性、穿通和击穿特性、亚阈值特性以及直流稳态特性等.通过这些模拟和分析计算,给出了沟道长度为0.18、0.15和0.1μm的薄膜全耗尽 SOI／MOS器件的设计方案,并根据该设计方案成功地研制出了性能良好的沟道长度为0.15μm的凹陷沟道 SOI器件.沟道长度为0.15μm薄膜全耗尽凹陷沟道SOI器件的亚阈值斜率为87mV/dec,击穿电压为1.6V,阈值电压为0.42V,电源电压为1.5V时的驱动电流为1.85mA,泄漏电流为0.5pA/μm沟道宽度.     

采用半背沟注入提高部分耗尽SOI nMOSFETs的漏源击穿电压

制备了采用半背沟注入的浮体和体接触部分耗尽SOI nMOSFETs.测试结果表明这样的器件相对于传统的部分耗尽SOI nMOSFETs来说,在提高击穿电压和延缓翘曲现象发生方面有良好的表现,并且背栅阈值电压没有太大的变化.数值模拟表明降低的电场有助于击穿特性的提高和翘曲现象的延缓.详细分析了提高击穿特性和延缓翘曲效应的原因.     

部分耗尽SOI体接触nMOS器件的关态击穿特性

分别采用具有硅化物和不具有硅化物的SOI工艺制成了部分耗尽SOI体接触nMOS晶体管.在体接触浮空和接地的条件下测量了器件的关态击穿特性.通过使用二维工艺器件模拟,并测量漏体结的击穿特性,详细讨论和分析了所制成器件击穿特性的差异和击穿机制.在此基础上,提出了一个提高PD-SOI体接触nMOS击穿特性的方法.     

亚100nm SOI器件的结构优化分析

分析了SOI器件各结构参数对器件性能的影响,给出了器件各结构参数的优化方向,找出了可行硅膜厚度和可行沟道掺杂浓度之间的设计容区.在部分耗尽与全耗尽SOI器件的交界处,阈值电压的漂移有一个峰值,在器件设计时应避免选用这一交界区.此外,随着硅膜厚度的减小,器件的泄漏电流随着沟道掺杂浓度的不同,有一个极小值.通过模拟分析发现,只要合理选择器件的结构参数,就能得到性能优良的SOI器件     

亚100nm SOI器件的结构优化分析

分析了SOI器件各结构参数对器件性能的影响,给出了器件各结构参数的优化方向,找出了可行硅膜厚度和可行沟道掺杂浓度之间的设计容区.在部分耗尽与全耗尽SOI器件的交界处,阈值电压的漂移有一个峰值,在器件设计时应避免选用这一交界区.此外,随着硅膜厚度的减小,器件的泄漏电流随着沟道掺杂浓度的不同,有一个极小值.通过模拟分析发现,只要合理选择器件的结构参数,就能得到性能优良的SOI器件.     

全耗尽SOI MOSFETs阈值电压解析模型

提出了一种新的全耗尽SOI MOSFETs阈值电压二维解析模型.通过求解二维泊松方程得到器件有源层的二维电势分布函数,氧化层-硅界面处的电势最小值用于监测SOI MOSFETs的阈值电压.通过对不同栅长、栅氧厚度、硅膜厚度和沟道掺杂浓度的SOI MOSFETs的MEDICI模拟结果的比较,验证了该模型,并取得了很好的一致性.     

对异型硅岛实现的厚膜全耗尽SOIMOSFET的模拟研究

本文提出了用异型硅岛实现的厚膜全耗尽(FD)SOI MOSFET的新结构,并分析了其性能与结构参数的关系.通过在厚膜SOI MOSFET靠近背栅的界面形成一个相反掺杂的硅岛,从而使得厚膜SOI MOSFET变成全耗尽器件.二维模拟显示,通过对异型硅岛的宽度、厚度、掺杂浓度以及在沟道中位置的分析与设计,厚膜SOI MOSFET不仅实现了全耗尽,从而克服了其固有的Kink效应,而且驱动电流也大大增加,器件速度明显提高,同时短沟性能也得到改善.模拟结果证明:优化的异型硅岛应该位于硅膜的底部中央处,整个宽度约为沟道长度的五分之三,厚度大约等于硅膜厚度的一半,掺杂浓度只要高出硅膜的掺杂浓度即可.重要的是,异型硅岛的设计允许其厚度、宽度、掺杂浓度以及位置的较大波动.可以看出,异型硅岛实现的厚膜全耗尽 SOI MOSFET 为厚膜SOI器件提供了一个更广阔的设计空间.     

电离辐射中SOI MOSFETs的背栅异常kink效应研究

采用10keV X射线研究了部分耗尽SOI MOSFETs的总剂量辐射效应.实验结果显示,在整个辐射剂量范围内,前栅特性保持良好;而nMOSFET和pMOSFET的背栅对数Id-Vg2曲线中同时出现了异常kink效应.分析表明电离辐射在埋氧/顶层硅(BOX/SOI)界面处产生的界面态陷阱是导致异常kink效应产生的原因.基于MEDICI的二维器件模拟结果进一步验证了这个结论.     

电离辐射中SOI MOSFETs的背栅异常kink效应研究

采用10keV X射线研究了部分耗尽SOI MOSFETs的总剂量辐射效应.实验结果显示,在整个辐射剂量范围内,前栅特性保持良好;而nMOSFET和pMOSFET的背栅对数Id-Vg2曲线中同时出现了异常kink效应.分析表明电离辐射在埋氧/顶层硅(BOX/SOI)界面处产生的界面态陷阱是导致异常kink效应产生的原因.基于MEDICI的二维器件模拟结果进一步验证了这个结论.     

Increased junction breakdown voltages in silicon-on-insulatordiodes

A junction breakdown model and the results of PISCES II simulations are presented for silicon-on-insulator (SOI) devices. This model shows the dependence of breakdown voltage in fully depleted (FD) SOI diode on the backgate bias, the properties of the buried oxide layer, and the device parameters. Breakdown in a thin FD SOI diode is quite different from that observed in a thicker, partially depleted (PD) diode. The analysis is supported by breakdown voltage measurements of separation by implantation of oxygen (SIMOX)-based SOI diodes, the results of which suggest that body breakdown is dominant in FD SOI diodes, and the junction curvature effect is dominant in PD SOI diodes. Furthermore, the results also show that breakdown voltage in the FD SOI diode is higher than their bulk-silicon counterpart and can be further increased by applying the appropriate backgate bias     

Influence of device engineering on the analog and RF performances of SOI MOSFETs

This work presents a systematic comparative study of the influence of various process options on the analog and RF properties of fully depleted (FD) silicon-on-insulator (SOI), partially depleted (PD) SOI, and bulk MOSFET's with gate lengths down to 0.08 /spl mu/m. We introduce the transconductance-over-drain current ratio and Early voltage as key figures of merits for the analog MOS performance and the gain and the transition and maximum frequencies for RF performances and link them to device engineering. Specifically, we investigate the effects of HALO implantation in FD, PD, and bulk devices, of film thickness in FD, of substrate doping in SOI, and of nonstandard channel engineering (i.e., asymmetric Graded-channel MOSFETs and gate-body contacted DTMOS).     

Hot carrier-induced SOI MOSFET degradation under AC stressconditions

The hot-carrier-induced device degradation in partially depleted silicon-on-insulator (SOI) devices has been investigated under AC stress conditions. The device degradation of both floating-body SOI devices and body contacted SOI devices have been measured and analyzed for different AC stress frequencies and gate bias voltages. Possible degradation mechanisms are suggested     

AC floating-body effects in submicron fully depleted (FD) SOInMOSFETs and the impact on analog applications

We report the impact of submicron fully depleted (FD) SOI MOSFET technology on device AC characteristics and the resultant effects on analog circuit issues. The weak DC kink and high frequency AC kink dispersion in FD SOI still degrade circuit performance in terms of distortion and low-frequency noise requirements. These issues raise concerns about FD devices for mixed-mode applications. Therefore, further device optimization such as source/drain engineering is still necessary to solve the aforementioned issues for FD SOI. On the other hand, partially depleted SOI MOSFET with body contact structures provide an alternative technology for RF/baseband analog applications     

Closed-form breakdown voltage model for PD SOI NMOS devices considering impact ionization of both parasitic BJT and surface MOS channel simultaneously

This paper reports a compact breakdown voltage model for partially depleted (PD) silicon-on-insulator (SOI) n-metal-oxide-semiconductor (NMOS) devices considering BJT/MOS impact ionization. Via the improved current conduction model considering BJT/MOS impact ionization this compact model provides an accurate prediction of the breakdown behavior of the PD SOI NMOS devices as verified by the experimental data and the MEDICI results. Based on the analytical model, when the gate voltage is lowered, the breakdown voltage decreases due to a stronger function of the parasitic BJT. In the subthreshold region, the breakdown voltage increases at a decreased gate voltage due to a weaker function of the parasitic BJT.     

γ射线辐照对130 nm部分耗尽SOI MOS器件栅氧经时击穿可靠性的影响

研究了射线辐照对130 nm部分耗尽（Partially Depleted,PD）绝缘体上硅（Silicon on Insulator,SOI）工艺MOS器件栅氧经时击穿（Time-Dependent Dielectric Breakdown,TDDB）寿命的影响。通过测试和对比辐照前后NMOS和PMOS器件的转移特性曲线、阈值电压、关态泄漏电流以及TDDB时间等电参数,分析了射线辐照对PD-SOI MOS器件TDDB可靠性的影响。结果表明:由于射线辐照在栅极氧化层中产生了带正电的氧化物陷阱电荷,影响了器件内部势垒的分布,降低了电子跃迁的势垒高度,导致了电子遂穿的正反馈作用增强,从而缩短了器件栅氧化层经时击穿时间,最终造成器件栅极氧化层的可靠性下降。     

Comprehensive study on low-frequency noise characteristics insurface channel SOI CMOSFETs and device design optimization for RF ICs

Low-frequency (LF) noise, a key figure-of-merit to evaluate device technology for RF systems on a chip, is a significant obstacle for CMOS technology, especially for partially depleted (PD) silicon-on-insulator (SOI) CMOS due to the well-known kink-induced noise overshoot. While the dc kink effect can be suppressed by either using body contact technologies or shifting toward fully depleted (FD) operation, the noise overshoot phenomena still resides at high frequency for either FD SOI or poor body-tied (BT) SOI CMOSFETs. In this paper, floating body-induced excess noise in SOI CMOS technology is addressed, including the impact from floating body effect, pre-dc kink operation, and gate overdrive, followed by the proposal of a universal LF excess noise model. As the physical mechanism behind excess noise is identified, this paper concludes with the suggestion of a device design methodology to optimize LF noise in SOI CMOSFET technology     

Temperature dependence of hot-carrier degradation in silicon-on-insulator dynamic threshold voltage MOS transistors

The authors analyze the influence of temperature on hot-carrier degradation of silicon-on-insulator (SOI) dynamic threshold voltage MOS (DTMOS) devices. Both low and high stress gate voltages are used. The temperature dependence of the hot-carrier effects in DTMOS devices is compared with those in SOI partially depleted (PD) MOSFETs. Possible physical mechanisms to explain the obtained results are suggested. This work shows that even if the stress gate voltage is low, the degradation of DTMOS devices stressed at high temperature could be significant.     

Investigation of the novel attributes of a fully depleted dual-material gate SOI MOSFET

The novel features of a fully depleted (FD) dual-material gate (DMG) silicon-on-insulator (SOI) MOSFET are explored theoretically and compared with those of a compatible SOI MOSFET. The two-dimensional numerical simulation studies demonstrate the novel features as threshold voltage roll-up and simultaneous transconductance enhancement and suppression of short-channel effects offered by the FD DMG SOI MOSFET. Moreover, these unique features can be controlled by engineering the workfunction and length of the gate material. This work illustrates the benefits of high-performance FD DMG SOI MOS devices over their single material gate counterparts and provides an incentive for further experimental exploration.