MAP译码器的免归一化处理信息更新算法

在不改变译码性能的条件下,为了加快最大后验概率(Maximum A Posteriori Probability,MAP)译码器状态信息更新的速度和降低算法的复杂度,提出了一种用于Turbo码的MAP译码器的免归一化处理算法.算法采用二进制补码加法器和减法器将MAP译码过程中的状态信息投影到一个归一化圆上,当状态信息更新时所有的状态信息在归一化圆上移动,通过保持归一化圆上状态信息的正确关系来计算似然比.归一化过程中不用搜索或估计状态信息的最大值,通过简化状态信息归一化过程加速了MAP译码器的状态信息更新并降低了复杂度.所提算法在与传统算法译码性能相同的情况下,可以降低36.2％的计算复杂度和17.4％的关键路径延迟,达到MAP译码器实现中的高速、低复杂度目标.     

MAP译码器嵌入式状态信息存储机制设计

嵌入式状态信息存储机制(ESMS)是一种用于turbo码的MAP译码算法以减少其状态信息对存储器容量需求的方法。对于LOG_MAP译码器,本文提出的ESMS从前向和后向状态信息更新过程中各取一个嵌入式状态信息,并用更新后的状态信息减掉嵌入式状态信息,从而减少对存储器的需求和计算复杂度。在状态信息更新过程中不保存的嵌入式状态的似然比信息通过网格中各状态的相对关系来保持。这样,嵌入式状态信息不用存储,且与用嵌入式状态信息相关的计算也可以省略。嵌入式状态存储机制可以使MAP译码器VLSI实现过程中减小面积和时延。     

一种适用于概率LDPC译码器的双路更新边缘存储器

针对采用传统边缘存储器结构的概率低密度奇偶校验(Low Density Parity Check,LDPC)译码器中仍存在锁存问题的现象,借鉴全并行Turbo译码器中的多路更新策略,提出了一种增强的变量节点和校验节点双路更新边缘存储器结构。利用双路更新结构引入的增强随机选择特性,可以显著降低概率迭代译码过程中的锁存现象。仿真分析表明,相比于单路更新结构,采用双路更新边缘存储器结构的概率LDPC译码器能够在误比特率接近10-4量级处获得0.4 dB左右的译码性能增益,同时也能够显著降低迭代译码周期数量,提升译码速率。     

一种合并状态度量计算的高效并行Turbo码译码器结构设计及FPGA实现

为满足无线通信中高吞吐、低功耗的要求,并行译码器的结构设计得到了广泛的关注。基于并行Turbo码译码算法,研究了前后向度量计算中的对称性,提出了一种基于前后向合并计算的高效并行Turbo码译码器结构设计方案,并进行现场可编程门阵列(field-programmable gate array,FPGA)实现。结果表明,与已有的并行Turbo码译码器结构相比,本文提出的设计结构使状态度量计算模块的逻辑资源降低50%左右,动态功耗在125 MHz频率下降低5.26%,同时译码性能与并行算法的译码性能接近。     

LTE-Advanced标准中一种基于反向重算的低存储容量Turbo码译码器结构设计

在LTE-Advanced标准中,为满足移动环境下的低功耗要求,低存储容量的译码器结构设计引起了广泛关注.本文在分解Turbo码网格图的基础上,研究了前向状态度量的反向重算方法,提出了一种基于反向重算的低存储容量译码器结构设计方案.在Log-MAP算法下研究了一种适合反向重算的修正雅可比对数式实现方法,推导了反向重算的数学表达式,并给出了实现结构.结果表明,所涉及的反向重算译码结构,以很小的冗余计算为代价将存储容量降低了50%,译码性能非常接近Log-MAP算法,在冗余计算复杂度、存储容量和译码性能指标上具有更好的均衡性.     

高速并行Turbo译码中的交织器技术研究

为了适应高速率通信系统的发展要求,Turbo码可采用并行译码的结构方式来降低时延.然而在并行Turbo码译码中,交织器的随机特性可能会导致多个数据同时写入同一个存储器,这就造成了存储器的访问冲突.如何设计出无冲突交织器是并行Turbo译码器的设计难点.文中对当前国内外的并行Turbo译码无冲突交织器设计方案进行了综述,对几种新的交织器分析研究.     

一种基于对称性的双向双二进制卷积Turbo码译码结构研究

该文提出了一种基于对称性的双向并行译码方案,用于提高802.16 m标准中双二进制卷积Turbo码(DB CTC)的译码速度。定义了分支度量矩阵以降低译码计算复杂度,定义了前向、后向因子矩阵,推导了前、后向度量递归计算中的对称性,并将其应用于前向、后向度量及后验概率对数似然比的双向并行计算中。构造了采用该方案的DB CTC译码器结构图,详细分析了迭代过程。以计算复杂度,存储空间,译码速度为指标考察了方案的性能,并给出了译码性能仿真曲线。分析表明,该双向并行的译码方法较常规方法提高了一倍的译码速度,而没有增加计算复杂度和存储空间。     

Turbo码的一种并行译码方案及相应的并行结构交织器研究

Turbo码基于MAP算法译码的递推计算所引入高的译码延迟限制了Turbo码在高速率数据传输中的应用。为了解决这个问题,该文提供了一种降低译码延迟的并行译码方法。并行处理方案的实现必须通过适当的交织以避免两个译码器对外信息读写的数据冲突。该文在分析了任意无冲突交织方式可能性的存在之后,给出了设计任意地适用于并行处理方案的S随机交织器的方法。仿真验证了并行译码方案的误比特性能。     

Turbo码高速译码器设计

Turbo码具有优良的纠错性能,被认为是最接近香农限的纠错码之一,并被多个通信行业标准所采用。Turbo码译码算法相比于编码算法要复杂得多,同时其采用迭代译码方式,以上2个原因使得Turbo码译码器硬件实现复杂,而且译码速度非常有限。从Turbo码高速译码器硬件实现出发,介绍Turbo码迭代译码的硬件快速实现算法以及流水线译码方式,并介绍利用Altera的Flex10k10E芯片实现该高速译码器硬件架构。测试和仿真结果表明,该高速译码器具有较高的译码速度和良好的译码性能。     

并行级联分组码的一种新的迭代译码算法

并行级联分组码比串行级联分组码具有更高的码率,基于LLR计算的Turbo迭代译码算法使其内外分量码均做到了软判决译码。通过引入校正因子a（m）,将接收信息与子译码器的输出软信息进行线性叠加反馈能在省去繁琐的LLR计算的情况下实现并行级联分组码的Turbo迭代译码。仿真研究表明,若将译码器的输出进行简单的相关运算,可进一步改善译码器性能。     

Memory-efficient path metric update method in map decoder implementation

A novel memory efficient path metric update is proposed for Maximum A Posteriori （MAP） decoder of turbo codes to reduce the memory requirement of state metric information calculation. For MAP decoder, the same memory can be shared by the forward and backward metrics with this metric update scheme. The forward and backward metrics update can be performed at the same time. And all of the extrinsic information can be calculated at the end of metric update. Therefore, the latency and area in the implementation will be reduced with the proposed metric update method.     

Low-power log-MAP decoding based on reduced metric memory access

Due to the powerful error correcting performance, turbo codes have been adopted in many wireless communication standards such as W-CDMA and CDMA2000. Although several low-power techniques have been proposed, power consumption is still a major issue to be solved in practical implementations. Since turbo decoding is classified as a memory-intensive algorithm, reducing memory accesses is crucial to achieve a low power design. To reduce the number of memory accesses for maximum a posteriori (MAP) decoding, this paper proposes an approximate reverse calculation method that can be implemented with simple arithmetic operations such as addition and comparison. Simulation results show that the proposed method applied to the W-CDMA standard reduces the access rate of the backward metric memory by 87% without degrading error-correcting performance. A prototype log-MAP decoder based on the proposed reverse calculation achieves 29% power reduction compared to a conventional decoder that does not use the reverse calculation.     

An intuitive justification and a simplified implementation of theMAP decoder for convolutional codes

An intuitive shortcut to understanding the maximum a posteriori (MAP) decoder is presented based on an approximation. This is shown to correspond to a dual-maxima computation combined with forward and backward recursions of Viterbi algorithm computations. The logarithmic version of the MAP algorithm can similarly be reduced to the same form by applying the same approximation. Conversely, if a correction term is added to the approximation, the exact MAP algorithm is recovered. It is also shown how the MAP decoder memory can be drastically reduced at the cost of a modest increase in processing speed     

A Memory‐Efficient Block‐wise MAP Decoder Architecture

Next generation mobile communication system, such as IMT‐2000, adopts Turbo codes due to their powerful error correction capability. This paper presents a block‐wise maximum a posteriori (MAP) Turbo decoding structure with a low memory requirement. During this research, it has been observed that the training size and block size determine the amount of required memory and bit‐error rate (BER) performance of the block‐wise MAP decoder, and that comparable BER performance can be obtained with much shorter blocks when the training size is sufficient. Based on this observation, a new decoding structure is proposed and presented in this paper. The proposed block‐wise decoder employs a decoding scheme for reducing the memory requirement by setting the training size to be N times the block size. The memory requirement for storing the branch and state metrics can be reduced 30% to 45%, and synthesis results show that the overall memory area can be reduced by 5.27% to 7.29%, when compared to previous MAP decoders. The decoder throughput can be maintained in the proposed scheme without degrading the BER performance.     

Modified maximum a posteriori decoding algorithm

A modified maximum a posteriori (MMAP) decoding algorithm that uses two extrinsic information values as the thresholds to determine the log-likelihood ratio, forward recursion probability and backward recursion probability is proposed. The MMAP requires less decoding time and complexity than an MAP decoder. Each probability of the proposed algorithm is derived and compared to that obtained using the MAP algorithm     

Double-Binary Circular Turbo Decoding Based on Border Metric Encoding

This brief presents an energy-efficient soft-input soft-output (SISO) decoder based on border metric encoding, which is especially suitable for nonbinary circular turbo codes. In the proposed method, the size of the branch memory is reduced to half and the dummy calculation is removed at the cost of a small-sized memory that holds encoded border metrics. Due to the infrequent accesses to the border memory and its small size, the energy consumed for SISO decoding is reduced by 26.2%. Based on the proposed SISO decoder and the dedicated hardware interleaver, a double-binary tail-biting turbo decoder is designed for the WiMAX standard using a 0.18-mum CMOS process, which can support 24.26 Mbps at 200 MHz.     

On the design of globally optimal communication strategies for real-time noisy communication systems with noisy feedback

A real-time communication system with noisy feedback is considered. The system consists of a Markov source, forward and backward discrete memoryless channels, and a receiver with limited memory. The receiver can send messages to the encoder over the backward noisy channel. The encoding at the encoder and the decoding, the feedback, and the memory update at the receiver must be done in real-time. A distortion metric that does not tolerate delays is given. The objective is to design an optimal real-time communication strategy, i.e., design optimal real-time encoding, decoding, feedback, and memory update strategies to minimize a total expected distortion over a finite horizon. This problem is formulated as a decentralized stochastic optimization problem and a methodology for its sequential decomposition is presented. This results in a set of nested optimality equations that can be used to sequentially determine optimal communication strategies. The methodology exponentially simplifies the search for determining an optimal real-time communication strategy.     

大约束度Viterbi译码器中路径存储单元的设计

维特比(Viterbi)译码器由于其优良的纠错性能,在通信领域有着十分广泛的应用。用FPGA实现Viterbi译码算法时,其硬件资源的消耗与译码速度始终是相互制约的两个方面,通过合理安排加比选单元和路径度量存储单元可有效缓解这一矛盾。基于基4算法所提出的同址路径度量存储管理方法能在提高译码速度同时有效降低译码器的硬件资源需求。     

A parallel MAP algorithm for low latency turbo decoding

To reduce the computational decoding delay of turbo codes, we propose a parallel algorithm for maximum a posteriori (MAP) decoders. We divide a whole noisy codeword into sub-blocks and use multiple processors to perform sub-block MAP decoding in parallel. Unlike the previously proposed approach with sub-block overlapping, we utilize the forward and backward variables computed in the previous iteration to provide boundary distributions for each sub-block MAP decoder. Our scheme depicts asymptotically optimal performance in the sense that the BER is the same as that of the regular turbo decoder