一种低功耗K频段低噪声放大器

基于0.13μm锗硅(SiGe)双极型互补金属氧化物(Bipolar Complementary Metal Oxide Semi-conductor,BiCMOS)工艺,设计制作了一种高增益低功耗K频段低噪声放大器(Low Noise Amplifier,LNA),通过优化晶体管尺寸及利用硅通孔设计高品质因数射极退化电感,降低了LNA噪声.实测结果表明,在1.6 V偏置条件下,该LNA在20 GHz的噪声系数等于1.94 dB,输入1 dB压缩点等于-29.6 dBm;18～21.3 GHz频率范围内,LNA增益大于23.3 dB,S11和S22均小于-10 dB.包含偏置电路功耗在内,芯片功耗仅21 mW,优于其他同等噪声系数的K频段SiGe BiCMOS LNA.该LNA可应用于卫星通信等K频段低功耗接收机系统.     

应用于智能水表的低功耗低噪声放大器设计

提出了基于多管并联结构的低功耗低噪声放大器(LNA),讨论了这种结构下噪声与功耗的相互关系,提出了低功耗LNA基于"优化区"概念的设计准则.提出的电路具有结构简单对称的特点.在0.35 μm CMOS工艺下进行PSPICE仿真测试.结果表明,新的低噪声放大器在(2.5) V电压下功耗仅为110 μW,等效输入噪声为16.5 nV/Hz~(1/2).与已发表的低噪声放大器比较,具有明显的低功耗特点.     

1.9 GHz CMOS低噪声放大器的结构分析与设计

对低噪声放大器(LNA)的结构及性能进行了详细的分析。采用SMIC 0.18μm射频CMOS工艺,设计了用于GSM1900无线接收机系统的两种不同结构的差动式LNA(电流复用式PMOS-NMOS LNA)和典型的NMOS LNA。利用Cadence-SpectreRFTM,对这两种结构的LNA进行了电路级仿真和对比分析。结果表明,在功耗相近时,PMOS-NMOS LNA能够提供比较大的电压增益,其噪声特性与NMOS LNA相近;NMOS LNA在线性度以及芯片面积上有更多的优势。     

一种超低功耗IR-UWB接收机射频前端

为满足无线体域网接收机超低功耗的要求,设计了一种3~5 GHz超低功耗非相关脉冲超宽带接收机射频前端电路,包括低噪声放大器(LNA)、有源巴伦和平方器。为了降低功耗,采用电流复用技术设计LNA和有源巴伦；同时设计了一种工作在亚阈值区域的全差分平方器,将基于吉尔伯特乘法器的平方器的功耗从mW级降低到μW级。此外,采用电容交叉耦合技术,提高了平方器的转换增益。基于SMIC 0.13 μm CMOS工艺的仿真结果显示,接收机射频前端在开关键控调制1 Mb/s脉冲速率下,其灵敏度达 -81 dBm,能量效率达0.42 nJ/pulse。     

医疗内窥检查超低功耗电感复用射频前端芯片设计

本文阐述了一种应用于医疗探测的工作在407～425MHz频段的电感复用射频前端芯片。本射频前端芯片由超低功耗电流复用LNA、Mixer和高发射效率PA构成。本文提出了一种新型的电感复用射频前端结构,通过接收机和发射机输入输出共用电感,不仅有效避免了双工器的使用降低了芯片成本,而且节省了片外元件的数量,满足了高集成度的应用要求。该射频前端芯片在0.18μm标准CMOS工艺下进行了流片,芯片面积0.43mm2。作为接收机和发射机使用时,射频前端功耗分别为0.45mA和1.53mA,是一款超低功耗、高集成度的射频前端芯片。     

X波段平衡式限幅低噪声放大器MMIC

为满足接收机的小型化需求，基于GaAs赝配高电子迁移率晶体管(PHEMT)工艺设计了一款用于8～12 GHz的平衡式限幅低噪声放大器(LNA)单片微波集成电路(MMIC)。将Lange电桥、限幅器、LNA集成在同一衬底上，Lange电桥采用异形设计，芯片比传统尺寸降低30%以上；限幅器级间采用电感匹配结构，提升MMIC的工作带宽；LNA采用并联负反馈、源极电感负反馈以及电流复用拓扑结构，实现超低功耗和良好的稳定性。芯片采用整体最优化设计，在片测试结果表明，在工作频带内，限幅LNA MMIC芯片的增益为(25±0.2)dB(去除1 dB斜率),噪声系数小于1.6 dB,总功耗小于100 mW,耐功率大于46 dBm,该芯片尺寸为2.8 mm×2.4 mm,充分体现了集成工艺的性能和尺寸优势。     

1GHz 0.5μm CMOS低噪声放大器的设计

从低噪声放大器(LNA)的设计原理出发,提出并设计了一种工作于1GHz的实用LNA.电路采用共源-共栅的单端结构,用HSPICE软件对电路进行分析和优化.模拟过程中选用的器件采用TSMC 0.5μm CMOS工艺实现.模拟结果表明所设计的LNA功耗小于15mW,增益大于10dB,噪声系数为1.87dB,IIP3大于10dBm,输入反射小于-50dB.可用于1GHz频段无线接收机的前端.     

应用于双频GPS接收机的CMOS低噪声放大器设计

结合双频GPS接收机的主要性能,提出了第一级低噪声放大器实现方案和电路实现方式.通过对影响单端LNA性能主要因素的分析,在电路结构和封装打线方式上进行改进,实现了低噪声系数高转换增益的单端LNA,从而提高了接收机灵敏度和噪声性能.     

一种应用于脉冲超宽带接收机的高增益LNA

基于SMIC 0.13 μm CMOS工艺,设计了一种应用于脉冲超宽带无线通信系统接收机的高增益低噪声放大器(LNA)。该LNA工作在6~9 GHz频段,单端输入,差分输出,采用电容交叉耦合与电流复用技术提高了增益,实现了低功耗性能。仿真结果表明,LNA电路工作在7.5 GHz中心频率时,增益高达46 dB,噪声系数为3.05 dB,输入端回波损耗为－12.5 dB,输出端回波损耗为－16.7 dB,在1.2 V电源供电下的核心消耗功耗为16 mW,核心电路面积仅为0.5 mm²。     

用于无线传感网络低功耗亚阈值CMOS低噪声放大器设计

设计一种工作在亚阈值区的低功耗CMOS低噪声放大器(LNA),用于无线传感网络.为了满足低功耗和高增益,设计使用共源共栅(cascode)结构并利用UMC 65nm工艺库进行仿真分析.仿真结果表明,在780MHz中心频率下,电路的增益大约34 dB,功耗仅为55μW,电源电压为1.2V.     

3.1～5.2GHz超宽带可变增益低噪声放大器设计

低噪声放大器是超宽带接收机系统中最重要的模块之一,设计了一种可应用于3.1～5.2GHz频段超宽带可变增益低噪声放大器。电路输入级采用共栅结构实现超宽带输入匹配,并引入电流舵结构实现了放大器的可变增益。仿真基于TSMC 0.18μm RF CMOS工艺。结果表明,在全频段电路的最大功率增益为10.5dB,增益平坦度小于0.5dB,噪声系数小于5dB,输入反射系数低于-15dB,在1.8V电源电压下,功耗为9mW。因此,该电路能够在低功耗超宽带射频接收机系统中应用。     

An 800-MHz–6-GHz Software-Defined Wireless Receiver in 90-nm CMOS

A software-defined radio receiver is designed from a low-power ADC perspective, exploiting programmability of windowed integration sampler and clock-programmable discrete-time analog filters. To cover the major frequency bands in use today, a wideband RF front-end, including the low-noise amplifier (LNA) and a wide tuning-range synthesizer, spanning over 800 MHz to 6 GHz is designed. The wideband LNA provides 18-20 dB of maximum gain and 3-3.5 dB of noise figure over 800 MHz to 6 GHz. A low 1/f noise and high-linearity mixer is designed which utilizes the passive mixer core properties and provides around +70 dBm IIP2 over the bandwidth of operation. The entire receiver circuits are implemented in 90-nm CMOS technology. Programmability of the receiver is tested for GSM and 802.11g standards     

Analysis and Design of Two Low-Power Ultra-Wideband CMOS Low-Noise Amplifiers With Out-Band Rejection

Two 3–5-GHz low-power ultra-wideband (UWB) low-noise amplifiers (LNAs) with out-band rejection function using 0.18- $mu{hbox{m}}$ CMOS technology are presented. Due to the Federal Communications Commission's stringent power-emission limitation at the transmitter, the received signal power in the UWB system is smaller than those of the close narrowband interferers such as the IEEE 802.11 a/b/g wireless local area network, and the 1.8-GHz digital cellular service/global system for mobile communications. Therefore, we proposed a wideband input network with out-band rejection capability to suppress the out-band properties for our first UWB LNA. Moreover, a feedback structure and dual-band notch filter with low-power active inductors will further attenuate the out-band interferers without deteriorating the input matching bandwidth in the second UWB LNA. The 55/48/45 dB maximum rejections at 1.8/2.4/5.2 GHz, a power gain of 15 dB, and 3.5-dB minimum noise figure can be measured while consuming a dc power of only 5 mW.      

一种用于卫星导航接收机的低噪声放大器设计

设计了一种可用于多模式卫星导航接收机的射频前端低噪声放大器,设计电路可在1.13～1.95 GHz工作,兼容了GPS,北斗及GLONOSS导航系统的工作频段。电路采用0.18 μm CMOS工艺实现。仿真结果表明,频带内S11和S22均在-10 dB以下,功率增益＞10 dB,带内最小噪声系数可达到2.2 dB,输出1 dB压缩点为-5.585 dBm,在1.8 V电源电压下,主体电路消耗12 mA电流。因此,该低频噪声放大器模块可满足当前各种导航系统的工作要求。     

A 6–9 GHz UWB balun-LNA employing current-reuse with preamplifier and CCC buffer

This paper presents a high-gain and low-power balun-LNA for ultra-wideband receiver operating in the upper band (6–9 GHz). Common gate (CG) preamplifier in front of the active balun can provide input matching and suppress noise from the follow-up stages. Active balun shares bias current with the CG stage to reduce power consumption. Capacitor-cross-coupled buffer is cascaded for signal amplitude and phase correction. The balun-LNA is fabricated in TSMC 130 nm CMOS technology and it consumes 5.5 mA current from a 1.3-V supply including buffer. This balun-LNA can achieve wideband gain from 6.5 to 9.0 GHz and the maximum gain is 23 dB. The input return loss is better than 20 dB from 6.5 to 9.0 GHz. The core area of the LNA is 0.53 mm². Simulated noise figure of the LNA is under 3.2 dB.     

A 2.1-6 GHz SiGe BiCMOS low-noise amplifier design for a multi-mode wideband receiver

A wideband low-noise amplifier (LNA) with ESD protection for a multi-mode receiver is presented.The LNA is fabricated in a 0.18-μm SiGe BiCMOS process,covering the 2.1 to 6 GHz frequency band.After optimized noise modeling and circuit design,the measured results show that the LNA has a 12 dB gain over the entire bandwidth,the input third intercept point (IIP3) is -8 dBm at 6 GHz,and the noise figure is from 2.3 to 3.8 dB in the operating band.The overall power consumption is 8 mW at 2.5 V voltage supply.     

A novel CMOS low-noise amplifier design for 3.1- to 10.6-GHz ultra-wide-band wireless receivers

An ultra-wideband (UWB) 3.1- to 10.6-GHz low-noise amplifier (LNA) employing a common-gate stage for wideband input matching is presented in this paper. Designed in a commercial 0.18-/spl mu/m 1.8-V standard RFCMOS technology, the proposed UWB LNA achieves fully on-chip circuit implementation, contributing to the realization of a single-chip CMOS UWB receiver. The proposed UWB LNA achieves 16.7/spl plusmn/0.8 dB power gain with a good input match (S11<-9 dB) over the 7500-MHz bandwidth (from 3.1 GHz to 10.6 GHz), and an average noise figure of 4.0 dB, while drawing 18.4-mA dc biasing current from the 1.8-V power supply. A gain control mechanism is also introduced for the first time in the proposed design by varying the biasing current of the gain stage without influencing the other figures of merit of the circuit so as to accommodate the UWB LNA in various UWB wireless transmission systems with different link budgets.     

An ultra-wideband CMOS low noise amplifier for 3-5-GHz UWB system

An ultra-wideband (UWB) CMOS low noise amplifier (LNA) topology that combines a narrowband LNA with a resistive shunt-feedback is proposed. The resistive shunt-feedback provides wideband input matching with small noise figure (NF) degradation by reducing the Q-factor of the narrowband LNA input and flattens the passband gain. The proposed UWB amplifier is implemented in 0.18-/spl mu/m CMOS technology for a 3.1-5-GHz UWB system. Measurements show a -3-dB gain bandwidth of 2-4.6GHz, a minimum NF of 2.3 dB, a power gain of 9.8 dB, better than -9 dB of input matching, and an input IP3 of -7dBm, while consuming only 12.6 mW of power.     

A Compact Wideband CMOS Low-Noise Amplifier Using Shunt Resistive-Feedback and Series Inductive-Peaking Techniques

A wideband low-noise amplifier (LNA) with shunt resistive-feedback and series inductive-peaking is proposed for wideband input matching, broadband power gain and flat noise figure (NF) response. The proposed wideband LNA is implemented in 0.18-mum CMOS technology. Measured results show that power gain is greater than 10 dB and input return loss is below -10 dB from 2 to 11.5 GHz. The IIP3 is about +3 dBm, and the NF ranges from 3.1 to 4.1 dB over the band of interest. An excellent agreement between the simulated and measured results is found and attributed to less number of passive components needed in this circuit compared with previous designs. Besides, the ratio of figure-of- merit to chip size is as high as 190 (mW^-1 /mm² ) which is the best results among all previous reported CMOS-based wideband LNA.     

0.5 V ultra-low power wideband LNA with forward body bias technique

An ultra-low power wideband CMOS low noise amplifier (LNA) fabricated in TSMC 0.18 μm RF CMOS process for sub 1 GHz applications is presented. The capacitive cross-coupled LNA with forwardbody- bias (FBB) technique is adopted to achieve wideband input impedance matching and low power, low noise factor. The LNA is tested in the frequency range of 400?900 MHz, and exhibits a voltage gain of 18.5?20.7 dB, and a noise figure of 2.95 dB, drawing only 0.385 mW from 0.5 V power supply.