Novel Bumping and Underfill Technologies for 3D IC Integration

In previous work, novel maskless bumping and no‐flow underfill technologies for three‐dimensional (3D) integrated circuit (IC) integration were developed. The bumping material, solder bump maker (SBM) composed of resin and solder powder, is designed to form low‐volume solder bumps on a through silicon via (TSV) chip for the 3D IC integration through the conventional reflow process. To obtain the optimized volume of solder bumps using the SBM, the effect of the volumetric mixing ratio of resin and solder powder is studied in this paper. A no‐flow underfill material named “fluxing underfill” is proposed for a simplified stacking process for the 3D IC integration. It can remove the oxide layer on solder bumps like flux and play a role of an underfill after the stacking process. The bumping process and the stacking process using the SBM and the fluxing underfill, respectively, for the TSV chips are carefully designed so that two‐tier stacked TSV chips are sucessfully stacked.     

Increasing the bonding strength of chips on flex substrates using thermosonic flip-chip bonding process with nonconductive paste

Thermosonic flip-chip bonding process with a nonconductive paste (NCP) was employed to improve the processability and bonding strength of the flip-chip onto flex substrates (FCOF). A non-conductive paste was deposited on the surface of the copper electrodes over the flex substrate, and a chip with eight gold bumps bonded onto the copper electrodes by the thermosonic flip-chip bonding process.For the chips and flex substrates assembly, ultrasonic power is important in the removal of some of the non-conductive paste on the surface of copper electrodes during thermosonic bonding. Accordingly, gold stud bumps in this study were directly bonded onto copper electrodes to form successful electrical paths between chips and the flex substrate. A particular ultrasonic power resulted in some metallurgical bonding between the gold bumps and the copper electrodes, increasing the bonding strength. The ultrasonic power was not only to remove the NCP from the copper electrodes, but also formed metallurgical bonds during the thermosonic flip-chip bonding process with NCP.In this study, the parameters of the bonding of chips onto flex substrates using thermosonic flip-chip bonding process with NCP were a bonding force of 4.9 N, a curing time of 40 s, a curing temperature of 140 °C and an ultrasonic power of 14.46 W. The processability and bonding strength of flip-chips on flex substrates using thermosonic bonding process with NCP was verified in this study. This process has great potential to be applied to the packaging of consumed electronic products.     

Reliability of assembly of chips and flex substrates using thermosonic flip-chip bonding process with a non-conductive paste

This study investigates the reliability of the assembly of chips and flex substrates using the thermosonic flip-chip bonding process with non-conductive paste (NCP). The high-temperature storage (HTS) test, the temperature cycling test (TCT), the pressure cooker test (PCT) and the high-temperature/high-humidity (HT/HH) test were conducted to examine the reliability of chips that are bonded on flex substrates. The environmental parameters used in the various reliability tests were consistent with the JEDEC standards. After the reliability tests, a peeling test was performed and the microstructure of the tested specimen observed to evaluate further the reliability.The bonding strength increased with the storage period in the HTS test. After the peeling test, a layer of copper electrodes was observed to be stuck on gold bumps over the fractured morphology of the chips when the chips and flex substrates were assembled using an ultrasonic power of 14.46 W, indicating that the bonding strength between the gold bumps and the copper electrodes was even higher than the adhesive strength of the layers that were deposited on the flex substrates. The HTS test yielded sufficient thermal energy to promote atomic interdiffusion between gold bumps and copper electrodes. Metallurgical bonding between the gold bump and the copper electrode occurred, improving the bonding strength. In the assembly of chips and flex substrates without the application of ultrasonic power in bonding process, the adhesive strength of NCP was highly reliable after HTS test, because the bonding strength was maintained after HTS test for various storage periods. The typical failure mode of PCT was interfacial delamination between NCP and flex substrates. Approximately 80% of the specimens exhibited full separation after PCT at 336 h when chips and flex substrates were assembled without applied ultrasonic power to the bonding process, revealing that the NCP cannot withstand the PCT and lost its adhesive strength. Applying an adequate ultrasonic power of 14.46 W in the bonding process not only improved the bonding strength, but also enabled the bonding strength to be maintained at high level after PCT. The high bonding strength was attributable to the strong bonding of the gold bumps on the copper electrodes after PCT for various storage periods. This experimental result demonstrates that ultrasonic power can increase the reliability of PCT on chips and flex substrates that were assembled with the NCP. The bonding strength of the gold bumps on the flex substrates did not change significantly after the TCT, revealing the great reliability of TCT on chips and flex substrates that were assembled using the thermosonic flip-chip bonding process with the NCP. The bonding strength of chips bonded to flex substrates increased with the storage periods of the HT/HH test if ultrasonic power was applied to bonding process. Neither delamination nor any defect at the bonding interface was observed. The reliability of the HT/HH test for chips bonded on flex substrates using the thermosonic flip-chip process with the NCP fulfills the requirements stated in the JEDEC standards.According to the experimental findings of various reliability tests, the chips that were bonded to flex substrates using the thermosonic bonding process with NCP met the JEDEC specifications; with the exception of the adhesive strength of NCP under PCT which must be improved.     

Interconnection Technology Based on InSn Solder for Flexible Display Applications

A novel interconnection technology based on a 52InSn solder was developed for flexible display applications. The display industry is currently trying to develop a flexible display, and one of the crucial technologies for the implementation of a flexible display is to reduce the bonding process temperature to less than 150°C. InSn solder interconnection technology is proposed herein to reduce the electrical contact resistance and concurrently achieve a process temperature of less than 150°C. A solder bump maker (SBM) and fluxing underfill were developed for these purposes. SBM is a novel bumping material, and it is a mixture of a resin system and InSn solder powder. A maskless screen printing process was also developed using an SBM to reduce the cost of the bumping process. Fluxing underfill plays the role of a flux and an underfill concurrently to simplify the bonding process compared to a conventional flip‐chip bonding using a capillary underfill material. Using an SBM and fluxing underfill, a 20 μm pitch InSn solder SoP array on a glass substrate was successfully formed using a maskless screen printing process, and two glass substrates were bonded at 130°C.     

Si/Glass激光键合的仿真及实验研究

对Si/Glass激光键合进行了有限元仿真,自主设计激光键合系统并进行了Si/Glass激光键合实验研究、测试与表征。以Si/Glass激光键合的二维传热解析模型为理论基础,应用有限元软件ANSYS仿真了激光功率20～48W时激光键合的三维温度场、键合熔融深度,并预测键合阈值功率为28 W。自主设计激光键合系统及实验方案,采用光斑直径150μm、功率30W的Nd:YAG连续激光实现了Si/Glass的良好激光键合。测试结果表明,激光键合强度最高为阳极键合的5.2倍,激光键合腔体气密性测试泄漏率平均值约9.29×10-9 Pa.m3/s,与阳极键合处于同一数量级。采用能谱分析(EDS)线扫描Si/Glass激光键合的界面材料成分,发现键合界面形成过渡层,激光功率30W时过渡层厚度9μm,与仿真结果吻合。     

Electrical and Mechanical Properties of Through-Silicon Vias and Bonding Layers in Stacked Wafers for 3D Integrated Circuits

Thermal stress issues in a three-dimensional (3D) stacked wafer system were examined using finite-element analysis of the stacked wafers. This paper elucidates the effects of the bonding dimensions on mechanical failure and the keep-away zone, where devices cannot be located because of the stress in the Si. The key factors in decreasing the thermal strain were the bonding diameter and thickness. When the bonding diameter decreased from 40 μm to 12 μm, the equivalent strain decreased by 83%. It is noteworthy that the keep-away zone also decreased from 17 μm to zero when the bonding diameter decreased from 40 μm to 12 μm. When the bonding thickness doubled, the equivalent strain decreased by 44%. The effects of the dimensions and arrangement of through-silicon vias (TSV) were also analyzed. Small TSV diameter and pitch are important to decrease the equivalent strain, especially when the amount of Cu per unit volume is fixed. When the TSV diameter and pitch decreased fourfold, the equivalent strain decreased by 70%. The effects of TSV height and the number of die stacks were not significant, because the underfill acted as a buffer against thermal strain.     

Study of the Au/In Reaction for Transient Liquid-Phase Bonding and 3D Chip Stacking

The latest three-dimensional (3D) chip-stacking technology requires the repeated stacking of additional layers without remelting the joints that have been formed at lower levels of the stack. This can be achieved by transient liquid-phase (TLP) bonding whereby intermetallic joints can be formed at a lower temperature and withstand subsequent higher-temperature processes. In order to develop a robust low-temperature Au/In TLP bonding process during which all solder is transformed into intermetallic compounds, we studied the Au/In reaction at different temperatures. It was shown that the formation kinetics of intermetallic compounds is diffusion controlled, and that the activation energy of Au/In reaction is temperature dependent, being 0.46 eV and 0.23 eV for temperatures above and below 150°C, respectively. Moreover, a thin Ti layer between Au and In was found to be an effective diffusion barrier at low temperature, while it did not inhibit joint formation at elevated temperatures during flip-chip bonding. This allowed us to control the intermetallic formation during the distinct stages of the TLP bonding process. In addition, a minimal indium thickness of 0.5 μm is required in order to enable TLP bonding. Finally, Au/In TLP joints of ∅40 μm to 60 μm were successfully fabricated at 180°C with very small solder volume (1 μm thickness).     

The application of flip-chip bonding interconnection technique on the module assembly of 10 Gbps laser diode

Flip chip bonding technique using Pb/In solder bumps was applied to packaging of a 10 Gbps laser diode (LD) submodule for high speed optical communication systems. The effect of the flip-chip bonding interconnection technique instead of conventional wire bonding was investigated for high speed broad band devices. The broad band performance of 10 Gbps LD submodule was simulated using SPICE S/W and compared with experimental results. In this simulation, the 10 Gbps LD was modeled in a parallel RC circuit. The values of R and C used for the equivalent circuit were 5ω and 1 pF, respectively. The LD was placed in series with a 18ω thin film resistor to prevent the impedance mismatch between the LD and a 25ω transmission line. The dependence of parasitic parameters on the small signal modulation bandwidth and the scattering parameters of the LD submodule was investigated and analyzed up to 20 GHz. A small signal modulation bandwidth of 14 GHz at 10 mA dc bias current and the clean modulation response up to 20 GHz were found for the flip-chip bonded submodule. The bandwidth of flip-chip bonded 10 Gbps LD submodule is wider than that of the wire-bonded LD submodule by a difference of 3.8 GHz.     

Fluxless Bonding of Large Silicon Chips to Ceramic Packages Using Electroplated Eutectic Au/Sn/Au Structures

A fluxless process of bonding large silicon chips to ceramic packages has been developed using a Au-Sn eutectic solder. The solder was initially electroplated in the form of a Au/Sn/Au multilayer structure on a ceramic package and reflowed at 430°C for 10 min to achieve a uniform eutectic 80Au-20Sn composition. A 9 mm × 9 mm silicon chip deposited with Cr/Au dual layers was then bonded to the ceramic package at 320°C for 3 min. The reflow and bonding processes were performed in a 50-mTorr vacuum to suppress oxidation. Therefore, no flux was used. Even without any flux, high-quality joints were produced. Microstructure and composition of the joints were studied using scanning electron microscopy with energy-dispersive x-ray spectro- scopy. Scanning acoustic microscopy was used to verify the joint quality over the entire bonding area. To employ the x-ray diffraction method, samples were made by reflowing the Au/Sn/Au structure plated on a package. This was followed by a bonding process, without a Si chip, so that x-rays could scan the solder surface. Joints exhibited a typical eutectic structure and consisted of (Au,Ni)Sn and (Au,Ni)₅Sn phases. This novel fluxless bonding method can be applied to packaging of a variety of devices on ceramic packages. Its fluxless nature is particularly valuable for packaging devices that cannot be exposed to flux such as sensors, optical devices, medical devices, and laser diodes.     

Cooling rate in diode laser bonding

Diode laser die bonding parameters were measured for the cases of slow cool and rapid cool die bonding processes. The thermal strain, solder composition and structure, thermal impedance, and bond strength of InP based diode lasers bonded to AlN chip carriers using pre-deposited Au-Sn solder were examined. Relative to the rapid cool process, the slow cool process was found on average: to induce greater strain in the laser chips; to exhibit a larger thermal impedance in the die bonds; to produce a rougher solder structure; and, to promote alloying of the solder material and chip carrier metallization.     

A Hermetic Seal Using Composite Thin-Film In/Sn Solder as an Intermediate Layer and Its Interdiffusion Reaction with Cu

A bonding joint between Cu metallization and evaporated In/Sn composite solder is produced at a temperature lower than 200°C in air. The effects of bonding temperature and duration on the interfacial bonding strength are studied herein. Cross sections of bonding joints processed at different bonding conditions were examined by scanning electron microscopy (SEM). The optimal condition, i.e., bonding temperature of 180°C for 20 min, was chosen because it gave rise to the highest average bonding strength of 6.5 MPa, and a uniform bonding interface with minimum voids or cracks. Good bond formation was also evidenced by scanning acoustic imaging. For bonding couples of patterned dies, a helium leak rate of 5.8 × 10⁻⁹ atm cc/s was measured, indicating a hermetic seal. The interfacial reaction between Cu and In/Sn was also studied. Intermetallic compounds (IMCs) such as AuIn₂, Cu₆Sn₅, and Cu₁₁In₉ were detected by means of x-ray diffraction analysis (XRD), and transmission electron microscopy (TEM) accompanied by energy-dispersive x-ray (EDX) spectroscopy. Chemical composition analysis also revealed that solder interlayers, Sn, and In were completely converted into IMCs by reaction with Cu. All the IMCs formed in the joints have remelting temperatures above 300°C according to the Cu-In, Cu-Sn, and Au-In phase diagrams. Therefore, the joint is able to sustain high service temperatures due to the presence of these IMCs.     

表面活化处理在激光局部键合中的应用

为了研究低热应力键合工艺,提出了一种将表面活化直接键合与激光局部键合相结合的键合技术。首先采用RCA溶液对键合片进行表面亲水活化处理,并在室温下成功地完成了预键合。然后在不使用任何夹具施加外力辅助的情况下,利用波长1064nm、光斑直径500μm、功率70W的Nd:YAG连续式激光器,实现了激光局部键合,并取得了6.3MPa~6.8MPa的键合强度。结果表明,这种以表面活化预键合代替加压的激光局部键合技术克服了传统激光键合存在的激光对焦困难,以及压力不匀易损害键合片和玻璃盖板等缺点,同时缩短了表面活化直接键合的退火时间,提高了键合效率。     

硅通孔技术的发展与挑战

3D堆叠技术近年来发展迅速,采用硅通孔技术(TSV)是3D堆叠封装的主要趋势.介绍了3D堆叠集成电路、硅通孔互连技术的研究现状、TSV模型;同时阐述了TSV的关键技术与材料,比如工艺流程、通孔制作、通孔填充材料、键合技术等;最后分析了其可靠性以及面临的挑战.TSV技术已经成为微电子领域的热点,也是未来发展的必然趋势,运用它将会使电子产品获得高性能、低成本、低功耗和多功能性.     

Experimental and numerical study of 3D stacked dies under forced air cooling and water immersion cooling

3D stacked die structure is a promising architecture to realize small feature size and enhance electronic performance. However, thermal performance in 3D stacked die has aroused extensive attention for its high density integration. In this paper, a stacked dummy die structure integrated with polyimide heater inside is presented to investigate the thermal behavior of 3D stacked dies. One-dimensional thermal resistance network is built and calculated to analyze thermal resistance distribution of the stacked dies. Under natural convection, the thermal resistance of convective heat transfer greatly influences total thermal resistance and limits heat dissipation ability of stacked dies. To significantly reduce the thermal resistance of convective heat transfer, forced air cooling and water immersion cooling have been applied in the stacked die structure. Experiment and numerical simulation have been conducted in this work. In the experiment, forced air cooling and water immersion cooling systems are set up to cool down the stacked die structure. The temperature dependence of the stacked die structure is obtained by thermocouples. The measured thermal resistances between junction and ambient environment of the stacked die structure decrease to 7.6 °C/W under forced air cooling and to 0.6 °C/W under water immersion cooling, respectively. Then heat dissipation abilities of forced convection cooling for the stacked die structure are analyzed. Simulation models are built for experimental validation and further thermal analysis. Temperature influences on the internal structure of the stacked dies with different power map are discussed. The simulation results can well capture the experimental results with 5.8% variation under forced air cooling and with 7.4% variation under water immersion cooling when total power of 3 W is applied.     

Interfacial Reaction and Die Attach Properties of Zn-Sn High-Temperature Solders

Interfacial reaction and die attach properties of Zn-xSn (x = 20 wt.%, 30 wt.%, and 40 wt.%) solders on an aluminum nitride–direct bonded copper substrate were investigated. At the interface with Si die coated with Au/TiN thin layers, the TiN layer did not react with the solder and worked as a good protective layer. At the interface with Cu, CuZn₅, and Cu₅Zn₈ IMC layers were formed, the thicknesses of which can be controlled by joining conditions such as peak temperature and holding time. During multiple reflow treatments at 260°C, the die attach structure was quite stable. The shear strength of the Cu/solder/Cu joint with Zn-Sn solder was about 30 MPa to 34 MPa, which was higher than that of Pb-5Sn solder (26 MPa). The thermal conductivity of Zn-Sn alloys of 100 W/m K to 106 W/m K was sufficiently high and superior to those of Au-20Sn (59 W/m K) and Pb-5Sn (35 W/m K).     

Study of thinned Si wafer warpage in 3D stacked wafers

3D (three-dimensional) wafer stacking technology has been developed extensively recently. One of the many technical challenges in 3D stacked wafers, and one of the most important, is wafer warpage. Wafer warpage is one of the root causes leading to process and product failures such as delamination, cracking, mechanical stresses, within wafer (WIW) uniformity and even electrical failure. In this study, the wafer warpage of thinned Si wafers in stacked wafers has been evaluated. Si wafer or glass was used as a thick substrate, and Cu or polyimide was used as the bonding material. The top Si wafer in the bonded stack was ground down to 20–100 μm, and wafer curvature was measured. Wafer curvature and how it relates to bonding material, substrate material of the stacked layers, and thickness of thinned Si wafer will be discussed.     

Ambient Temperature Ultrasonic Bonding of Si-Dice Using Sn-3.5wt.%Ag

Ultrasonic bonding of Si-dice to type FR-4 printed circuit boards (PCB) with Sn-3.5wt.%Ag solder at ambient temperature was investigated. The under-bump metallization (UBM) on the Si-dice comprised Cu/Ni/Al from top to bottom with thicknesses of 0.4 μm, 0.4 μm, and 0.3 μm, respectively. The pads on the PCBs consisted of Au/Ni/Cu with thicknesses of 0.05/5/18 μm, sequentially from top to bottom. Solder was supplied as Sn-3.5wt.%Ag foil rolled to 100 μm thickness, and inserted in the joints. The ultrasonic bonding time was varied from 0.5 s to 3.0 s, and the ultrasonic power was 1400 W. The experimental results showed that reliable joints could be produced between the Si-dice and the PCBs with Sn-3.5wt.%Ag solder. The joint breaking force of “Si-die/solder/FR-4” increased with bonding times up to 2.5 s with a maximum value of 65 N. A bonding time of 3.0 s proved to be excessive, and resulted in cracks along the intermetallic compound between the UBM and solder, which caused a decrease in the bond strength. The intermetallic compound produced by ultrasonic bonding between the UBM and solder was confirmed to be (Cu, Ni)₆Sn₅. An erratum to this article can be found at     

Selective bonding and encapsulation for wafer-level vacuum packaging of MEMS and related micro systems

A laser-assisted bonding technique is demonstrated for low temperature region selective processing. A continuous wave carbon dioxide (CO₂) laser (λ=10.6 μm) is used for solder (Pb37/Sn63) bonding of metallized silicon substrates (chips or wafers) for MEMS applications. Laser-assisted selective heating of silicon led to the reflow of an electroplated, or screen-printed, intermediate solder layer which produced silicon–solder–silicon joints. The bonding process was performed on fixtures in a vacuum chamber at an air pressure of 10⁻³ Torr to achieve fluxless soldering and vacuum encapsulation. The bonding temperature at the sealing ring was controlled to be close to the reflow temperature of the solder. Pull test results showed that the joint was sufficiently strong. Helium leak testing showed that the leak rate of the package met the requirements of MIL-STD-883E under optimized bonding conditions and bonded packages survived thermal shock testing. The testing, based on a design of experiments method, indicated that both laser incident power and scribe velocity significantly influenced bonding results. This novel method is especially suitable for encapsulation and vacuum packaging of chips or wafers containing MEMS and other micro devices with low temperature budgets, where managing stress distribution is important. Further, released and encapsulated devices on the sealed wafers can be diced without damaging the MEMS devices at wafer level.     

Non-conductive film with Zn-nanoparticles (Zn-NCF) for 40 μm pitch Cu-pillar/Sn–Ag bump interconnection

Non-conductive film with Zn nano-particles (Zn-NCF) is an effective solution for fine-pitch Cu-pillar/Sn–Ag bump interconnection in terms of manufacturing process and interfacial reliability. In this study, NCFs with Zn nano-particles of different acidity, viscosity, and curing speed were formulated and diffused Zn contents in the Cu pillar/Sn–Ag bumps were measured after 3D TSV chip-stack bonding. Amount of Zn diffusion into the Cu pillar/Sn–Ag bumps increased as the acidity of resin increased, as the viscosity of resin decreased, as the curing speed of resin decreased, and as the bonding temperature increased. Diffusion of Zn nano-particles into the Cu pillar/Sn–Ag bumps are maximized when the resin viscosity became lowered and the solder oxide layer was removed. To analyze the effects of Zn-NCF on IMC reduction, IMC height depending on aging time was measured and corresponding activation energies for IMC growth were calculated. For the evaluation of joint reliabilities, test vehicles were bonded using NCFs with 0 wt%, 1 wt%, 5 wt%, and 10 wt% of Zn nano-particles and aged at 150 °C up to 500 h. NCF with 10 wt% Zn nano-particle showed remarkable suppression in Cu₆Sn₅ and (Cu,Ni)₆Sn₅ IMC compared to NCFs with 0 wt%, 1 wt%, and 5 wt% of Zn nano-particles. However, in terms of Cu₃Sn IMC suppression, which is the most critical goal of this experiment NCFs with 1 wt%, 5 wt%, and 10 wt% showed an equal amount of IMC suppression. As a result, it was successfully demonstrated that the suppression of Cu–Sn IMCs was achieved by the addition of Zn nano-particles in the NCFs resulting an enhanced reliability performance in the Cu/Sn–Ag bumps bonding in 3D TSV interconnection.     

Silicon layer transfer using wafer bonding and debonding

Two experiments were performed that demonstrate an extension of the ion-cut layer transfer technique where a polymer is used for planarization and bonding. In the first experiment hydrogen-implanted silicon wafers were deposited with two to four microns low-temperature plasma-enhanced tetraethoxysilane (TEOS). The wafers were then bonded to a second wafer, which had been coated with a spin-on polymer. The bonded pairs were heated to the ion-cut temperature resulting in the transfer of a 400 nm layer silicon. The polymer enabled the bonding of an unprocessed silicon wafer to the as-deposited TEOS with a microsurface roughness larger than 10 nm, while the TEOS provided sufficient stiffness for ion cut. In the second experiment, an intermediate transfer wafer was patterned and vias were etched through the wafer using a 25% tetramethylammonium hydroxide (TMAH) solution and nitride as masking material. The nitride was then stripped using dilute hydrofluoric acid (HF). The transfer wafer was then bonded to an oxidized (100 nm) hydrogen-implanted silicon wafer. After ion-cut annealing a silicon-on-insulator (SOI) wafer was produced on the transfer wafer. The thin silicon layer of the SOI structure was then bonded to a third wafer using a spin-on polymer as the bonding material. The sacrificial oxide layer was then etched away in HF, freeing the thin silicon from the transfer wafer. The result produced a thin silicon-on-polymer structure bonded to the third wafer. These results demonstrate the feasibility of transferring a silicon layer from a wafer to a second intermediate “transfer” or “universal” reusable substrate. The second transfer step allows the thin silicon layer to be subsequently bonded to a potential third device wafer followed by debonding of the transfer wafer creating stacked three-dimensional structures.