3D堆叠技术及TSV技术

介绍了3D堆叠技术及其发展现状,探讨了W2W(Wafer to wafer)及D2W(Die to wafer)等3D堆叠方案的优缺点,并重点讨论了垂直互连的穿透硅通孔TSV(Through silicon via)互连工艺的关键技术,探讨了先通孔、中通孔及后通孔的工艺流程及特点,介绍了TSV的市场前景和发展路线图。3D堆叠技术及TSV技术已经成为微电子领域研究的热点,是微电子技术及MEMS技术未来发展的必然趋势,也是实现混合集成微系统的关键技术之一。     

TSV的工艺缺陷诊断与分析

随着3D集成封装的发展,硅通孔(TSV)成为实现3D堆叠中最有前景的技术之一.通过通孔和微凸点实现上下堆叠IC之间的垂直电连接,先进的TSV技术能够满足3D SIP异构集成、高速宽带、小尺寸及高性能等要求.然而,作为新型互连技术,TSV技术面临许多工艺上的困难和挑战,其可靠性没有得到充分的研究和保证.识别缺陷、分析失效机理对TSV三维集成器件的设计、生产和使用等各环节的优化和改进具有重要作用.对不同形状、不同深宽比的TSV通孔边界层进行了微观物理分析,对通孔形状、边界层均匀性等方面进行了评价,分析了各种工艺缺陷形成的物理机制以及可能带来的失效影响.最后根据其产生的原因提出了相应的改进措施.     

硅通孔TSV关键 降低成本和解决工艺路线

芯片工艺流程微缩和低介电值材料的限制,3D堆叠技术被视为能否以较小尺寸制造高效能芯片的关键,而硅通孔(TSV)可通过垂直导通整合晶圆堆叠的方式,达到芯片间的电路互连,有助于以更低的成本,提高系统的整合度与效能,是实现集成电路3D化的重要途径。未来,TSV的应用将取决于制造成本的进一步降低,业界对TSV发展途径的认识统一。     

3D-TSV技术——延续摩尔定律的有效通途

对于堆叠器件的3-D封装领域而言,硅通孔技术(TSV)是一种新兴的技术解决方案.将器件3D层叠和互连可以进一步加快产品的时钟频率、降低能耗和提高集成度.为了在容许的成本范围内跟上摩尔定律的步伐,在主流器件设计和生产过程中采用三维互联技术将会成为必然.介绍了TSV技术的潜在优势,和制约该技术发展的一些不利因素及业界新的举...     

3D堆叠封装硅通孔结构的电-热-结构耦合分析

硅通孔(TSV)技术作为三维封装的关键技术,其可靠性问题受到广泛的关注。基于ANSYS平台,通过有限元方法,对3D堆叠封装的TSV模型进行了电-热-结构耦合分析,并进一步研究了不同的通孔直径、通孔高度以及介质隔离层SiO_2厚度对TSV通孔的电流密度、温度场及热应力分布的影响。结果表明:在TSV/微凸点界面的拐角处存在较大的电流密度和等效应力,容易引起TSV结构的失效;增大通孔直径、减小通孔长度可以提高TSV结构的电-热-机械可靠性;随着SiO_2层厚度的增加,通孔的最大电流密度增大而最大等效应力减小,需要综合考虑合理选择SiO_2层厚度。     

三维叠层DRAM封装中硅通孔开路缺陷的模拟

采用硅通孔(TSV)技术的三维堆叠封装,是一种很有前途的解决方案,可提供微处理器低延迟,高带宽的DRAM通道.然而,在3D DRAM电路中,大量的TSV互连结构,很容易产生开路缺陷和耦合噪声,从而导致了新的测试挑战.通过大量的模拟研究.本文模拟了在三维DRAM电路的字线与位线中出现的TSV开路缺陷的故障行为,它作为有效...     

后摩尔时代的封装技术

介绍了在高性能的互连和高速互连芯片(如微处理器)封装方面发挥其巨大优势的TSV互连和3D堆叠的三维封装技术。采用系统级封装(SiP)嵌入无源和有源元件的技术,有助于动态实现高度的3D-SiP尺寸缩减。将多层芯片嵌入在内核基板的腔体中;采用硅的后端工艺将无源元件集成到硅衬底上,与有源元件芯片、MEMS芯片一起形成一个混合集成的器件平台。在追求具有更高性能的未来器件的过程中,业界最为关注的是采用硅通孔(TSV)技术的3D封装、堆叠式封装以及类似在3D上具有优势的技术,并且正悄悄在技术和市场上取得实实在在的进步。随着这些创新技术在更高系统集成中的应用,为系统提供更多的附加功能和特性,推动封装技术进入后摩尔时代。     

3D TSV测试的挑战和潜在解决方案(英文)

3D硅通孔技术增加电路密度、降低功耗、提高带宽的优势在业内已得到广泛的认可。随着3D TSV技术的迅速发展,对于测试成本的优化就显得尤为突出,现有的测试方法已提出了很多挑战3D TSV技术的解决方案。提出了一种不同的应对3D TSV测试技术挑战的完整的3DTSV测试解决方案,其中某些方面涉及到3D TSV测试的前沿技术,而且也是唯一面向3D TSV测试特定的解决方案。最后,给出了一些采用完整3D TSV测试中其余的挑战。     

新型的3D堆叠封装制备工艺及其实验测试

为了满足超大规模集成电路(VLSI)芯片高性能、多功能、小尺寸和低功耗的需求,采用了一种基于贯穿硅通孔(TSV)技术的3D堆叠式封装模型.先用深反应离子刻蚀法(DRIE)形成通孔,然后利用离子化金属电浆(IMP)溅镀法填充通孔,最后用Cu/Sn混合凸点互连芯片和基板,从而形成了3D堆叠式封装的制备工艺样本.对该样本的接触电阻进行了实验测试,结果表明,100 μm2Cu/Sn混合凸点接触电阻约为6.7 mΩ高90 μm的斜通孔电阻在20～30mΩ该模型在高达10 GHz的频率下具有良好的机械和电气性能.     

尔必达宣布开始销售采用TSV技术制作的DDR3 DRAM样品芯片

日本尔必达公司27日宣布已经开始销售采用硅通孔互连技术(TSV)制作的DDR3 SDRAM三维堆叠芯片的样品。这款样品的内部由四块2Gb密度DDR3 SDRAM芯片通过TSV三维堆叠技术封装为一块8Gb密度DDR3 SDRAM芯片(相当1GB容量),该三维芯片中还集成了接口功能芯片。     

Scaling trends of power noise in 3-D ICs

Power supply noise in three-dimensional integrated circuits (3-D ICs) considering scaled CMOS and through silicon via (TSV) technologies is the focus of this paper. A TSV and inductance aware cell-based 3-D power network model is proposed and evaluated. Constant TSV aspect ratio and constant TSV area penalty scaling, as two scenarios of TSV technology scaling, are discussed. A comparison of power noise among via-first, via-middle, and via-last TSV technologies with CMOS scaling is also presented. When the TSV technology is a primary bottleneck in high performance 3-D ICs, an increasing TSV area penalty should be adopted to produce lower power noise. As a promising TSV technology, via-middle TSVs are shown to produce the lowest power noise with CMOS technology scaling.     

三维集成大功率同步整流器的研究与设计

实现同步整流能够有效提高次级整流效率,并且有利于实现电源模块的小型化.将同步整流器中的控制电路和整流桥分别制作在两层芯片上,然后堆叠两层芯片并通过TSV实现层间信号互连,不仅能进一步提高集成度,还能有效降低引线延迟和功耗.设计了一种大功率同步整流器,仿真实现了输出电压为5V、最大输出电流为13.38A、输出电压和输出电...     

三维集成封装中的TSV互连工艺研究进展

为顺应摩尔定律的增长趋势,芯片技术已来到超越"摩尔定律"的三维集成时代。电子系统进一步小型化和性能提高,越来越需要使用三维集成方案,在此需求推动下,穿透硅通孔(TSV)互连技术应运而生,成为三维集成和晶圆级封装的关键技术之一。TSV集成与传统组装方式相比较,具有独特的优势,如减少互连长度、提高电性能并为异质集成提供了更宽的选择范围。三维集成技术可使诸如RF器件、存储器、逻辑器件和MEMS等难以兼容的多个系列元器件集成到一个系统里面。文章结合近两年的国外文献,总结了用于三维集成封装的TSV的互连技术和工艺,探讨了其未来发展方向。     

基于TSV转接板的3D SRAM单粒子多位翻转效应

为了研究硅通孔(TSV)转接板及重离子种类和能量对3D静态随机存储器(SRAM)单粒子多位翻转(MBU)效应的影响,建立了基于TSV转接板的2层堆叠3D封装SRAM模型,并选取6组相同线性能量传递(LET)值、不同能量的离子(¹¹B与^4He、²⁸Si与¹⁹F、⁵⁸Ni与²⁷Si、⁸⁶Kr与⁴⁰Ca、¹⁰⁷Ag与⁷⁴Ge、¹⁸¹Ta与¹³²Xe)进行蒙特卡洛仿真。结果表明,对于2层堆叠的TSV 3D封装SRAM,低能离子入射时,在Si路径下,下堆叠层SRAM多位翻转率比上堆叠层高,在TSV(Cu)路径下,下堆叠层SRAM多位翻转率比Si路径下更大;具有相同LET值的高能离子产生的影响较小。相比2D SRAM,在空间辐射环境中使用基于TSV转接板技术的3D封装SRAM时,需要进行更严格的评估。     

Through-Silicon via Interconnection for 3D Integration Using Room-Temperature Bonding

One approach to 3D technology is chip stacking using through-silicon vias (TSVs). Interconnects in a 3D assembly are potentially much shorter than in a 2D configuration, allowing for faster system speed and lower power consumption. However, it is extremely important to use cost-effective process technologies in practical use. Therefore, in our study, we propose a basic concept for interconnecting stacked chips with TSVs using a cost-effective process technology. The principal feature is to use a “mechanical-caulking” technique, which has been used widely in the mechanical-engineering field, enabling 3D interconnections between stacked chips. This makes it possible to interconnect them by only applying compressive force at room temperature. This paper presents the results obtained by using mechanical-caulking connections at room temperature accomplished by manufacturing a prototype of a chip-stacked package with TSV interconnections. A 3D-SiP composed of an existing MCU, an interposer, and an SDRAM chip with TSV interconnections was also manufactured. However, a customized design, assuming TSV interconnections in the existing MCU, needs to be introduced for practical use to achieve ${rm SiO}_{2}$ etching with shorter turn around time (TATs) and high TSV yields of more than 99%.      

Thinned wafer multi-stack 3DI technology

Wafer scale 3DI technology, so-called wafer-on-a-wafer (WOW), characterized by thinned-wafer stacking and Cu multi-level interconnects, has been developed, and revealed that seven-level multi-wafer stacking is possible. The WOW process differs from the chip-on-a-chip and chip-on-a-wafer processes and can be used for wafer-scale bulk processes, enabling manufacturing from transistor to 3D stacking using wafers. Wafers are thinned down to 20-μm and bonded to the base wafer following back-to-face stacking. Through-silicon-via (TSV) holes with a diameter of 30 μm are formed and etched-off until the lower electrode of Au which is patterned on the underneath wafer. Titanium (Ti) and titanium-nitride (TiN) are formed on a TSV hole as a barrier metal and electrode for the electrochemically plated Cu (ECP-Cu). After ECP-Cu deposition, surface planarization is performed using Surface Planer™. Those wafers are used as a base wafer and multi-stacking is carried out repeatedly. The vertical connection between Cu of TSV and Au is therefore connected with a self-aligned contact and without a bump electrode. The electrical properties of the 242-chain contacts within the wafer were measured and no open failure was found. Adopting the thinned substrates eliminates deep silicon etching, and TSV filling which take a long process time, and reduces the residual stress on the Cu plug. Wafers can be stacked as much as possible in accordance with the degree of integration, and this is expected to be a low-cost and high-integration technology for post-scaling.     

Analysis of 3D TSV Vertical Interconnection Using Pre-applied Nonconductive Films

Much research has been carried out to realize through-silicon via (TSV) technology for three-dimensional (3D) chip stacking packaging. A vertical chip interconnection method using Cu/Sn-Ag bumps and nonconductive films (NCFs) is one of the most promising approaches for 3D TSV vertical interconnection. In this work, the relationship between the viscosity of pre-applied NCFs and loading forces was investigated to predict the gap change between a TSV chip and a substrate chip. Existing theories of squeeze flow are adapted to predict the gap change of a real TSV chip and a substrate chip during TSV bonding using a simplified model. The real gaps measured during bonding of test dies were matched to check the validity of the prediction model. Considering the thixotropy of NCFs, the prediction well matched the real gap changes between bumped TSV chips and substrate chips during bonding.     

Collective laser‐assisted bonding process for 3D TSV integration with NCP

Laser‐assisted bonding (LAB) is an advanced technology in which a homogenized laser beam is selectively applied to a chip. Previous researches have demonstrated the feasibility of using a single‐tier LAB process for 3D through‐silicon via (TSV) integration with nonconductive paste (NCP), where each TSV die is bonded one at a time. A collective LAB process, where several TSV dies can be stacked simultaneously, is developed to improve the productivity while maintaining the reliability of the solder joints. A single‐tier LAB process for 3D TSV integration with NCP is introduced for two different values of laser power, namely 100 W and 150 W. For the 100 W case, a maximum of three dies can be collectively stacked, whereas for the 150 W case, a total of six tiers can be simultaneously bonded. For the 100 W case, the intermetallic compound microstructure is a typical Cu‐Sn phase system, whereas for the 150 W case, it is asymmetrical owing to a thermogradient across the solder joint. The collective LAB process can be realized through proper design of the bonding parameters such as laser power, time, and number of stacked dies.