一种具有高填充因数和动态数字双采样技术的CMOS图像传感器

介绍了基于0.35μm工艺设计的单片CMOS图像传感器芯片.该芯片采用有源像素结构,像素单元填充因数可达到43%,高于通常APS结构像素单元30%的指标.此外还设计了一种数字动态双采样技术,相对于传统的双采样技术(固定模式噪声约为0.5%),数字动态双采样技术具有更简洁的电路结构和更好抑制FPN噪声的效果.传感器芯片通过MPW计划采用Chartered 0.35μm数模混合工艺实现.实验结果表明芯片工作良好,图像固定模式噪声约为0.17%.     

A New CMOS Image Sensor with a High Fill Factor and the Dynamic Digital Double Sampling Technique

介绍了基于0.35μm工艺设计的单片CMOS图像传感器芯片.该芯片采用有源像素结构,像素单元填充因数可达到43%,高于通常APS结构像素单元30%的指标.此外还设计了一种数字动态双采样技术,相对于传统的双采样技术(固定模式噪声约为0.5%),数字动态双采样技术具有更简洁的电路结构和更好抑制FPN噪声的效果.传感器芯片通过MPW计划采用Chartered 0.35μm数模混合工艺实现.实验结果表明芯片工作良好,图像固定模式噪声约为0.17%.     

基于0.35 μm工艺设计的APS CMOS图像传感器

介绍了一种基于CHRT公司0.35 μm工艺而设计的CMOS图像传感器.该图像传感器采用APS像素结构,像素阵列256×256,包含有列放大器、阵列扫描、串行接口、控制逻辑和ADC等模块.该图像传感器采用动态数字双采样(DDDS)的新方法消除FPN噪音,并已经通过MPW采用CHRT 0.35 μm salicide 2P4M工艺流片.     

一种6T像素全局曝光CMOS图像传感器

提出了一种基于6T像素结构的全局曝光CMOS图像传感器。通过采用PPD结构的6T像素、高复位电平和低阈值器件,提高了动态范围,并优化设计了像素单元的版图,使之获得较高的填充系数;模拟读出电路部分,通过采用双采样、增益放大和减小列级固定模式噪声(FPN)处理,以及对列选控制电路进行优化,减小了对全局PGA的运放设计要求。芯片的工作频率为20MHz,动态范围为66dB,实现了全局曝光方式CMOS图像传感器的设计。     

基于双积分模拟重构大动态范围CIS系统研究

提出一种采用列共用模拟重构电路和双积分三采样工作时序的CMOS图像传感器(CIS)系统架构,可实现光电响应曲线压缩和像素固定模式噪声(FPN)消除,提高传感器动态范围到83 dB,使成像质量提高.该结构具有与单采样相同的像素阵列,仅增加很小的处理电路.改进的工作时序优化了长积分、短积分和信号处理的时序分配.系统控制由FPGA实现.功能和数模混合仿真验证表明,方案是可行的.     

高动态科学级CMOS相机设计与成像分析

为了满足高动态范围高灵敏度的全局曝光模式下成像系统的需求,基于CIS-2521科学级CMOS图像传感器设计了一个相机系统,通过分析CIS-2521芯片像素读出结构特点,通过芯片内部模拟相关双采样与FPGA片内数字域相关双采样完成相关四采样算法,列向噪声去除效果明显。通过设计曲线拟合双增益通道图像数据合成输出,保证了系统成像有较高输出动态范围。相机常温下输出图像峰值信噪比达62.9dB,采用半导体制冷后输出图像峰值信噪比74.3dB。根据EMVA1288标准实测相机动态范围达到78.2dB,设计的相机系统实现了每秒50帧2 560×2 160像素,16bit深度高清晰度高动态范围图像的实时全局曝光成像输出,能够满足低照度条件下的高帧频高动态范围成像的需求。     

低噪声CMOS图像传感器技术研究综述

文章总结了低噪声CMOS图像传感器代表性关键技术的最新研究进展。从CMOS图像传感器架构及各模块设计的角度,介绍了有源像素结构和图像传感器架构,分析了广泛采用的像素内源跟随CMOS图像传感器读出电路及其噪声等效模型,重点介绍了低噪声CMOS图像传感器关键技术,包括共享参考像素差分共源放大器技术、相关多采样技术、像素内斩波技术,以及相关技术的电路级实现方式。     

一种实时CIS暗电流校正方法及系统实现

为了减弱暗电流对互补型金属氧化物半导体(CMOS)图像传感器(简称CIS)图像质量的影响,本文基于图像处理的方式提出了一种实时校正CMOS图像传感器暗电流的方法,并在一个最高帧频(50f/s)的4晶体管像素结构CMOS图像传感器内集成了该方法的电路。测试结果表明,该方法获得了准确的暗电平,并且实时消除了75%以上暗电流引入的固定模式噪声(FPN,fixed pat-tern noise),大大改善了图像质量。     

包含交流耦合CTIA与数字CDS的CMOS图像传感器设计

设计了一种带隔直电容的交流耦合CTIA像元电路与数字相关双采样（DCDS）结构的CMOS图像传感器系统。在传统的CTIA像元电路中增加隔直电容,通过控制光电二极管的偏压,达到减小光电二极管暗电流的目的;同时采用片外数字CDS结构,通过在片外实现复位信号与像元积分信号的量化结果在数字域的减法,可以减小图像传感器像元的复位噪声和固定图案噪声（FPN）。基于0.35 m标准CMOS工艺对此CMOS图像传感器进行流片,像元阵列为256256,像元尺寸为16 m16 m。测试结果表明交流耦合CTIA像元电路可以将光电二极管的偏压控制在零偏点附近,此时其暗电流最小;采用了数字CDS结构后,图像传感器像元的时域噪声及固定图案噪声均有不同程度降低。     

混合域实现图像块矩阵变换的CIS像素读出噪声分析

为了研究双存储像素的读出噪声对混合域实现图像块矩阵变换的CMOS图像传感器(CIS)产生的误差影响,对其进行噪声分析。结合双存储像素的工作时序,对实现图像块矩阵变换过程中由于多次采样和双路存储而增加的kTC噪声、源跟随器的1/f噪声和热噪声进行分析并建立数学模型,总结出双存储像素读出噪声对一次块矩阵变换的误差影响。以二维离散余弦变换为例,通过CHRT 0.35 m标准CMOS工艺电路仿真并结合matlab/simulink对比验证,得出增大存储电容、减小源跟随器宽长比可以降低由于像素读出噪声引起的误差。结果证明,此方法可以有效降低噪声,指导电路设计。     

Novel Logarithmic Active Pixel Sensor with High Dynamic Range and High Output Swing

The logarithmic response complementary metal oxide semiconductor （CMOS） image sensor provides a wide dynamic range, but its drawback is the lack of simple fixed pattern noise（FPN） cancellation scheme. Designed is a novel logarithmic active pixel sensor（APS） with high dynamic range and high output swing. Firstly, the operation principle of mixed-model APS is introduced. The pixel can work in three operation modes by choosing the proper control signals. Then, FPN sources of logarithmic APS are analyzed, and double-sampled technique is implemented to reduce FPN. Finally, according to the simulation results, layout is designed and has passed design rule check（DRC）, electronic rule eheck（ERC） and layout versus schematic（LVS） verifications, and the post-simulation results are basically in agreement with the simulation results. Dynamic range of the new logarithmic APS can reach about 140 dB; and the output swing is about 750 inV. Results show that by using double sampled technique, most FPN is eliminated and the dynamic range is enhanced.     

A logarithmic response CMOS image sensor with on-chip calibration

CMOS image sensors with logarithmic response are attractive devices for applications where a high dynamic range is required. Their strong point is the high dynamic range. Their weak point is the sensitivity to pixel parameter variations introduced during fabrication. This gives rise to a considerable fixed pattern noise (FPN) that deteriorates the image quality unless pixel calibration is used. In the present work a technique to remove the FPN by employing on-chip calibration is introduced, where the effect of threshold voltage variations in pixels is cancelled. An image sensor based on an active pixel structure with five transistors has been designed, fabricated, and tested. The sensor consists of 525×525 pixels measuring 7.5 μm×10 μm, and is fabricated in a 0.5-μm CMOS process. The measured dynamic range is 120 dB while the FPN is 2.5% of the output signal range     

Design and evaluation of current-mode image sensors in CMOS-technology

Three different current-mode-output CMOS image sensor structures comprising of a pixel cell and an appropriate readout circuit have been analyzed and compared with regard to their noise behavior, fixed-pattern noise (FPN), and the dynamic range. First, a standard integrating pixel cell with a readout circuit containing a voltage-to-current converter is proposed. Second, a pixel cell based on a switched current cell is analyzed. The third sensor cell uses a feedback loop to control the reverse bias voltage of the photodiode to reduce the settling time of the pixel cell and the influence of the photodiodes's dark current. The necessary amplifier is partly located in the pixel cell and partly in the readout circuit. In all sensors, correlated double sampling is used to suppress the FPN.     

Research on Column FPN and Black Level Calibration in Large Array CMOS Image Sensor

A technical investigation, research and im-plementation is presented to correct column fixed pattern noise and black level in large array Complementary metal oxide semiconductor (CMOS) image sensor. Through making a comparison among reported solution, and give large array CMOS image sensor design and considerations, according to our previous analysis on non-ideal factor and error source of piecewise Digital to analog converter (DAC) in multi-channels, an improving accurate piecewise DAC with adaptive switch technique is developed. The research theory has verified by a high dynamic range and low column Fixed pattern noise (FPN) CMOS image sensor prototype chip, which consisting of 8320×8320 pixel array was designed and fabricated in 55nm CMOS 1P4M standard process. The chip active area is 48mm×48mm with a pixel size of 5.7μm×5.7μm. The measured results achieved a high intrinsic dynamic range of 75dB, a low FPN and black level of 0.06％, a low photo response non-uniformity of 1.5％ respectively, and an excellent raw sample image taken by the prototype sensor.     

A High-Speed, High-Sensitivity Digital CMOS Image Sensor With a Global Shutter and 12-bit Column-Parallel Cyclic A/D Converters

This paper presents a high-speed, high-sensitivity 512times512 CMOS image sensor with column parallel cyclic 12-bit ADCs and a global electronic shutter. Each pixel has a charge amplifier for high charge-to-voltage conversion gain despite of using a large-size photodiode, and two sample-and-hold stages for the global shutter and fixed pattern noise (FPN) canceling. High-speed column-parallel cyclic ADC arrays with 12-bit resolution having a small layout size of 0.09 mm ² are integrated at both sides of image array. A technique for accelerating the conversion speed using variable clocking and sampling capacitance is developed. A digital gain control function using 14-bit temporal digital code is also set in the column parallel ADC. The fabricated chip in 0.25-mum CMOS image sensor technology achieves the full frame rate in excess of 3500 frames/s. The in-pixel charge amplifier achieves the optical sensitivity of 19.9 V/lxmiddots. The signal full scale at the pixel output is 1.8 V at 3.3-V supply and the noise level is measured to be 1.8mV_rms, and the resulting signal dynamic range is 60 dB     

一种应用于CMOS图像传感器数字双采样ADC的PGA电路

提出了一种应用于CMOS图像传感器数字双采样模数转换器(ADC)的可编程增益放大器(PGA)电路。通过增加失调采样电容,采集PGA运放和电容失配引入的失调电压,在PGA复位阶段和放大阶段进行相关双采样和放大处理,通过数字双采样ADC将两个阶段存储电压量化,并在数字域做差,降低了PGA电路引入的固定模式噪声。采用0.18μm CMOS图像传感器专用工艺进行仿真,结果表明:在输入失调电压-30~30mV变化区间,提出的PGA的输出失调电压可以降低到1mV以下,相比传统PGA输出失调电压随输入失调电压单倍线性关系而言大大降低了列固定模式噪声。     

320×240 Pixels CMOS Digital Image Sensor with Wide Dynamic Range

A 320×240 CMOS image sensor is demonstrated,which is implemented by a standard 0.6 μm 2P2M CMOS process.For reducing the chip area,each 2×2-pixel block shares a sample/hold circuit,analog-to-digital converter and 1-b memory.The 2×2 pixel pitch has an area of 40 μm×40 μm and the fill factor is about 16%.While operating at a low frame rate,the sensor dissipates a very low power by power-management circuit making pixel-level comparators in an idle state.A digital correlated double sampling,which eliminates fixed pattern noise,improves SNR of the sensor, and multiple sampling operations make the sensor have a wide dynamic range.