红外探测器背景抑制读出结构设计研究

长波红外焦平面探测器一般工作在高背景下,信号电流小于背景电流,器件本身暗电流也较大,信号读出时积分电容极易饱和,这都不利于获得理想的信噪比.通过在读出电路输入级中增加电流抑制结构,可有效提高积分时间,改善动态范围和对比度.本文介绍了红外焦平面读出电路中几种典型的背景电流及暗电流抑制技术,依次叙述不同结构背景及暗电流抑制的实现原理,并比较各个结构的优缺点,针对不同电路结构的特点,通过典型电路仿真分析,确定了它们在各种红外焦平面读出电路输入级中的应用范围.     

红外探测器背景抑制读出结构设计研究

长波红外焦平面探测器一般工作在高背景下，信号电流小于背景电流，器件本身暗电流也较大，信号读出时积分电容极易饱和，这都不利于获得理想的信噪比。通过在读出电路输入级中增加电流抑制结构，可有效提高积分时间，改善动态范围和对比度。本文介绍了红外焦平面读出电路中几种典型的背景电流及暗电流抑制技术，依次叙述不同结构背景及暗电流抑制的实现原理，并比较各个结构的优缺点，针对不同电路结构的特点，通过典型电路仿真分析，确定了它们在各种红外焦平面读出电路输入级中的应用范围。     

抑制背景电流的红外焦平面单元读出电路

随着非制冷红外焦平面阵列技术的发展,红外读出电路的设计变得越来越重要。设计了一种带有背景电流抑制功能的红外焦平面单元读出电路,该读出电路在改进后的第一代开关电流电路的基础上实现背景电流抑制功能。详细阐述了该系统电路的整体架构和工作原理,并用Spectre仿真软件实现了电路的仿真。结果表明该方案可以抑制背景电流,实现红外读出功能。     

红外探测器背景抑制读出结构设计研究

长波红外焦平面探测器一般工作在高背景下，信号电流小于背景电流，器件本身暗电流也较大，信号读出时积分电容极易饱和，这都不利于获得理想的信噪比。通过在读出电路输入级中增加电流抑制结构，可有效提高积分时间，改善动态范围和对比度。本文介绍了红外焦平面读出电路中几种典型的背景电流及暗电流抑制技术，依次叙述不同结构背景及暗电流抑制的实现原理，并比较各个结构的优缺点，针对不同电路结构的特点，通过典型电路仿真分析，确定了它们在各种红外焦平面读出电路输入级中的应用范围。     

具有分时背景抑制功能的单元电路设计

介绍了一种具有分时背景抑制功能的单元电路,该单元电路适合于大规模2D红外焦平面阵列.在减电流电路设计中,自级联管采用长沟道设计,工作在强反型区,各单元电路的减去电流不易受到工艺偏差的影响,有效地降低了具有分时背景抑制功能的单元电路间的背景抑制非均匀性(BSUN).在背景电流为100 nA,积分时间为2.7 ms,减去电流为3.28 μA,构成自级联管的两个晶体管阈值电压的最大失配均为10 mV时,具有分时背景抑制功能的单元电路间的BSNU为3.310%.     

基于门控多周期积分的背景抑制读出电路

在空间遥感领域,波长在3?m～5?m的中红外焦平面探测器大都工作在高背景环境下,信号电流远小于背景电流。为解决当前信号淹没于背景这一突出问题,设计了一种采用门控多周期积分结构实现的背景抑制功能的读出电路。该电路在抑制背景电流(包括暗电流)的同时能有效降低噪声,提高有效积分时间,增大输出信号动态范围。经Spectre仿真软件验证了电路设计的正确性。背景电流输入范围为0 nA～110 nA,能够有效读出2.5 nA～25 nA之间的信号电流,电路输出摆幅大于2 V。该电路的设计不仅能解决当前工程中的关键问题,还对今后高性能大面阵红外焦平面高背景弱信号探测具有重要的指导意义。     

基于逐元暗电流抑制的红外探测器读出电路研究

在航天应用领域,大部分中长波红外探测器都工作在高背景下.由于线列碲镉汞(HgCdTe)红外探测器本身的暗电流较大且各像元的暗电流具有很大的非均匀性,采用常规读出电路方案时的输出信号动态范围过小,甚至部分像元的信号电压也无法读出.采用将电压 电流转换和电流存储单元相结合的方法,设计了一种具有逐元背景抑制功能的中波红外探测器线列读出电路.该方法不仅可以抑制不同像元的暗电流,而且还可以有效提高电路的信噪比,并可增大输出信号的动态范围.电路测试结果表明,在90 K低温下,电路输出摆幅为2V,输出电压的非均匀性下降了70％,因此该研究对中长波红外探测器的工程化设计具有重要的指导意义.     

具有背景抑制功能的长波红外读出电路

为了提高红外焦平面检测目标的灵敏度，目标辐射产生的载流子应尽可能长时间保持，同时应尽可能减少热激发和背景辐射激发的比例。高背景条件下长波红外读出电路的积分电容较快饱和，且长波红外探测器暗电流的非均匀性会影响焦平面的固定图形噪声。基于共模背景抑制结构以及长波碲镉汞探测器暗电流分析的基础上，设计了具有非均匀性矫正的背景抑制电路。传统的背景抑制电路采用单一共模背景抑制或差模背景抑制。差模背景抑制模块的高精度背景记忆一般在小范围区间内。本文背景抑制结构采用共模背景抑制与差模背景抑制相结合，可以在较大的背景噪声范围内有效地降低固定图形噪声以及增大动态范围。该背景抑制结构中共模背景抑制采用电压-电流转换法，差模背景抑制采用电流存储型背景抑制结构。差模背景抑制通过背景记忆时信号放大，背景抑制时信号缩小来提高背景抑制精度。电路采用标准CMOS工艺流片。测试结果表明:读出电路的FPN值为2.08 mV。未开启背景抑制时，焦平面FPN值为48.25 mV。开启背景抑制后，焦平面FPN值降至5.8 mV。基于探测器的暗电流非均匀分布，计算其理论FPN值为40.9 mV。长波红外焦平面输出信号的RMS噪声在0.6 mV左右。     

太赫兹量子阱探测器的暗电流抑制电路研究

主要研究了太赫兹量子阱探测器读出电路中的暗电流抑制模块。首先从理论上分析了太赫兹量子阱探测器产生暗电流和光电流的原理。由于太赫兹量子阱探测器中电子输运行为非常复杂,难以通过理论推导建立精确等效电路模型的解析表达式。通过对太赫兹量子阱探测器的电流电压实验数据进行拟合,提出压控电流源等效电路模型。利用此模型设计读出电路信号源及暗电流抑制模块,结合读出电路进行仿真验证电路模型的准确性。发现与传统暗电流抑制电路相比,压控电流源电路模型能够在器件工作偏压变化时对其暗电流进行精确抑制,提高读出电路性能,因此更适合作为太赫兹量子阱探测器读出电路的暗电流抑制模块。     

红外焦平面读出电路技术及发展趋势

从红外焦平面技术的发展背景出发,论述了读出电路在红外焦平面信号传输中的作用并介绍其基本框图,讨论了CCD读出电路和CMOS读出电路各自的特点,并分析了国内外红外焦平面读出电路的现状,最后提出了红外焦平面阵列读出电路今后的研究方向.     

Smart TDI readout circuit for long-wavelength IR detector

A smart time delay and integration (TDI) readout circuit is suggested which performs background suppression, cell-to-cell non-uniformity compensation, and dead pixel correction. Using the smart TDI readout circuit, the integration capacitor area occupying almost the whole area of a unit-cell can be reduced to one-fifth and transimpedance gain can increase by five times. From measurement results, it is found that the skimming current error for a few hundred nA background current is < 1.25 nA corresponding to LSB/2 of ADC and the non-uniformity introduced by cell-to-cell background current variation is reduced to 1.02 nA     

High-performance CMOS buffered gate modulation input (BGMI) readoutcircuits for IR FPA

A new CMOS current readout structure for the infrared (IR) focal-plane-array (FPA), called the buffered gate modulation input (BGMI) circuit, is proposed in this paper. Using the technique of unbalanced current mirror, the new BGMI circuit can achieve high charge sensitivity with adaptive current gain control and good immunity from threshold-voltage variations. Moreover, the readout dynamic range can be significantly increased by using the threshold-voltage-independent current-mode background suppression technique. To further improve the readout performance, switch current integration techniques, shared-buffer biasing technique, and dynamic charging output stage with the correlated double sampling circuit are also incorporated into the BGMI circuit. An experimental 128×128 BGMI readout chip has been designed and fabricated in 0.8 μm double-poly-double-metal (DPDM) n-well CMOS technology. The measurement results of the fabricated readout chip under 77 K and 5 V supply voltage have successfully verified both readout function and performance improvement. The fabricated chip has the maximum charge capacity of 9.5×10⁷ electrons, the transimpedance of 2.5×10⁹ Ω at 10 nA background current, and the arrive power dissipation of 40 mW. The uniformity of background suppression currents can be as high as 99%. Thus, high injection efficiency, high charge sensitivity, large dynamic range, large storage capacity, and low noise can be achieved In the BGMI circuit with the pixel size of 50×50 μm². These advantageous characteristics make the BCMI circuit suitable for various IR FPA readout applications with a wide range of background currents     

A current memory cell with switch feedthrough reduction by errorfeedback

A new switch feedthrough suppressing current memory cell, capable of accurately memorizing low current levels is presented. The scheme operates by feeding back a fraction of the error current to the storage node whose voltage is adjusted so that the error is reduced to zero. Using the feedback compensation scheme, absolute current error of less than 0.1% was achieved even at ultra-low current levels of 10 nA. The negative feedback circuit consumes negligibly low power and can be laid in a very small area. With this scheme, memory accuracy is traded for error correction speed, a feature common to all feedback-based switch feedthrough reduction schemes. The feedback compensated current memory cell can be used for low-power high-background infrared focal-plane readout electronics featuring in-pixel background suppression     

New dark current suppression CMOS readout circuit with novel CDS structure for large format QWIP FPA

A new Dark Current Suppression (DCS) CMOS readout circuits for large format Quantum-Well-Infrared Photo-detector (QWIP) Focal-Plane-Array (FPA) with novel CorrelatedDouble-Sampling (CDS) structure based on dynamic source-follower are proposed, which can overcome the drawbacks of the present techniques, such as sensitive to the non-uniformity of the QWIP materials, poor readout noise features, low frame frequency, limited injection efficiency and dynamic range, etc. The dummy is adopted to realize dark current suppression, while the cascode current mirror (with current ratio of 1:10) can increase charge sensitivity and reduce integration time. Through the novel CDS structure, the output waveform is boxcar, and the frame frequency is increased. Simulation results demonstrate that, in high background sense, the proposed DCS circuit can suppress the dark current, achieve good readout performance, such as low power consumption, high charge sensitivity, high resolution, large dynamic range, and insensitive to the non-uniformity of the QWIP materials.     

CMOS Readout Circuit with New Background Suppression Technique for Room-Temperature Infrared FPA Applications

A high-performance CMOS readout integrated circuit (ROIC) with a new temperature and power supply independent background current and dark current suppression technique for room-temperature infrared focal plane array applications is proposed. The structure is composed of an improved switched current integration stage, a new current-mode background suppression circuit, and a high linearity, high voltage swing output stage. An experimental readout chip has been designed and fabricated using the Chartered 0.35 μm CMOS process. Both the function and performance of the proposed readout circuit have been verified by experimental results. The test results show that the detector bias error in this structure is less than 0.1 mV. The input resistance is close to an ideal value of zero, and the injection efficiency is almost 100%. The output voltage linearity of the designed circuit is more than 99%. The background suppression level is tunable between 8 nA–1.5 μA, and the background suppression uniformity is as high as 100%. A unit-cell occupies a 10 μm × 15 μm area and consumes less than 0.07 mW power.     

Ultra‐Low‐Power Differential ISFET/REFET Readout Circuit

A novel ultra‐low‐power readout circuit for a pH‐sensitive ion‐sensitive field‐effect transistor (ISFET) is proposed. It uses an ISFET/reference FET (REFET) differential pair operating in weak‐inversion and a simple current‐mode metal‐oxide semiconductor FET (MOSFET) translinear circuit. Simulation results verify that the circuit operates with excellent common‐mode rejection ability and good linearity for a single pH range from 4 to 10, while only 4 nA is drawn from a single 1 V supply voltage.     

CMOS readout circuit allowing microbolometer arrays to operate without temperature stabilisation

A new CMOS readout circuit that controls the non-uniformity of microbolometer arrays as a function of operating temperature change is described. This circuit provides a nonlinear bias current for operating temperature using a MOS transistor that is operated in the subthreshold region. This approach allows microbolometer arrays to operate without temperature stabilisation up to an operating temperature change of approximately 40K.