重离子成角度入射导致的锗硅异质结双极晶体管单粒子效应三维数值仿真

针对国产锗硅异质结双极晶体管(SiGe HBTs),采用TCAD仿真,建立SiGe HBT单粒子效应三维损伤模型,研究重离子成角度入射SiGe HBT时单粒子效应电荷收集的关键因素。选择几个典型入射位置和不同入射角度进行数值仿真,通过分析器件结构和仿真结构来研究电荷收集机制。结果表明,无论是离子入射位置如何,只要离子径迹穿过器件的灵敏体积,就会引起大量电荷收集。电荷收集量不仅与离子径迹在SiGe HBT敏感体积内的长度有关,同时也受到浅槽隔离以及离子径迹和电极之间的距离的影响。此项工作对SiGe HBT空间实际应用,并进一步提出加固方案提供了理论依据。     

SiGe HBT单粒子瞬态TCAD仿真研究

借助于TACD数值仿真,对具有交叉指状结构的锗硅异质结双极型晶体管(SiGeHBT)中由重离子辐射诱导的单粒子瞬态(SET)效应展开了详细的研究.首先分析了重离子辐射诱导的电势和场强的变化,阐明了SiGe HBT中单粒子瞬态机制.然后,通过对比重离子入射至器件不同位置时各电极的瞬态电流和感生电荷的收集情况,确定了集电极/衬底(CS)结及附近区域为SiGe HBT单粒子瞬态的敏感区域.结果表明相对于集电极和衬底的电荷收集,基极和发射极收集的电荷可忽略不计.此外,各电极的瞬态电流和电荷收集还具有明显的位置依赖性.上述结果可为SiGe HBT单粒子效应的抗辐射加固提供有力的指导依据.     

锗硅异质结双极晶体管空间辐射效应研究进展

异质结带隙渐变使锗硅异质结双极晶体管(SiGe HBT)具有良好的温度特性,可承受-180~+200 ℃的极端温度,在空间极端环境领域具有诱人的应用前景。然而,SiGe HBT器件由于材料和工艺结构的新特征,其空间辐射效应表现出不同于体硅器件的复杂特征。本文详述了SiGe HBT的空间辐射效应研究现状,重点介绍了国产工艺SiGe HBT的单粒子效应、总剂量效应、低剂量率辐射损伤增强效应以及辐射协同效应的研究进展。研究表明,SiGe HBT作为双极晶体管的重要类型,普遍具有较好的抗总剂量和位移损伤效应的能力,但单粒子效应是制约其空间应用的瓶颈问题。由于工艺的不同,国产SiGe HBT还表现出显著的低剂量率辐射损伤增强效应响应和辐射协同效应。     

基于三维模型的InGaP/GaAs HBT单粒子效应仿真

为全面评估航天型号用元器件的抗辐射性能,对InGaP/GaAs异质结双极晶体管(Heterojunction Bipolar Transistor,HBT)的单粒子效应进行了仿真研究。首先,介绍了空间辐射环境中重离子诱发器件产生单粒子瞬态脉冲的机理。然后,建立了InGaP/GaAs HBT器件三维仿真模型,并利用蒙特卡罗方法模拟了不同能量的C、F、Cl、Br、I等重离子在器件中的射程和LET值。最后,基于ISE-TCAD仿真软件对器件的单粒子瞬态脉冲电流曲线进行了仿真和分析。结果表明:重离子在器件中产生的集电极瞬态脉冲电流可达几百微安,集电极瞬态脉冲电流与重离子的能量成反比,与离子的原子序数成正比。由此可知,InGaP/GaAs HBT器件对单粒子效应比较敏感,且对不同重离子的敏感程度不同。这可以为航天型号用元器件的设计选型和可靠性评估提供技术支撑。     

锗硅异质结双极器件单粒子效应与加固技术研究进展

锗硅异质结双极晶体管(Silicon-Germanium Heterojunction Bipolar Transistors, SiGe HBT)具有高速、高增益、低噪声、易集成等多种优势,广泛应用于高性能模拟与混合信号集成电路。同时,基区能带工程带来的优异低温特性以及良好的抗总剂量、抗位移损伤能力使其拥有巨大的空间极端环境应用潜力。然而,SiGe HBT固有的器件结构使其对单粒子效应极为敏感,并严重制约了SiGe电路综合抗辐射能力的提升。针对上述问题,综述了SiGe HBT单粒子效应及加固技术的研究进展,详细阐述了SiGe HBT单粒子效应的基本原理,分析了影响单粒子效应敏感性的关键因素,并对比了典型加固方法取得的效果,从而为抗辐射SiGe工艺开发和电路设计提供参考。     

一种抑制单粒子瞬态响应的SiGe HBT工艺加固技术仿真

基于0.13 μm SiGe BiCMOS工艺,开展了无深槽NPN SiGe HBT工艺和器件仿真。模拟了带深P阱SiGe HBT的制备过程、常规电学特性和重离子单粒子效应。该器件与常规器件相比表现出更优的单粒子瞬态(SET)特性,在关态的SET响应峰值下降了80%,在最大特征频率工作点的SET响应峰值下降了27%,瞬态保持时间也大幅减小。使用深N阱和深P阱隔离同时抑制了集电区-衬底结的漂移载流子收集和衬底扩散载流子收集的过程,极大地提高了器件的SET性能。     

深亚微米CMOS反相器的单粒子瞬态效应研究

针对小尺寸CMOS反相器的单粒子瞬态效应,分别采用单粒子效应仿真和脉冲激光模拟试验两种方式进行研究。选取一种CMOS双反相器作为研究对象,确定器件的关键尺寸,并进行二维建模,完成器件的单粒子瞬态效应仿真,得到单粒子瞬态效应的阈值范围。同时,开展脉冲激光模拟单粒子瞬态效应试验,定位该器件单粒子瞬态效应的敏感区域,捕捉不同辐照能量下器件产生的单粒子瞬态脉冲,确定单粒子瞬态效应的阈值范围,并与仿真结果进行对比分析。     

极端低温下SiGe HBT器件研究进展

系统地介绍了极端低温下SiGe HBT器件的研究进展。在器件级,分析了能带工程对SiGe HBT器件特性的影响,分析了极端低温下器件的直流、交流、噪声特性的变化,以及器件的特殊现象。在电路级,分析了基于SiGe HBT的运算放大器、低噪声放大器和电压基准源电路的低温工作特性。研究结果表明,SiGe HBT器件在低温微电子应用中具有巨大潜力。     

晶体管栅形状对单粒子瞬态脉冲特性的影响研究

通过三维器件模拟仿真,研究了基于CMOS 0.18μm工艺下标准条形栅和环形栅结构MOS晶体管的单粒子瞬态响应.研究结果表明,单粒子轰击条形栅器件与环形栅器件产生的单粒子瞬态脉冲特性具有非常大的区别.分析了栅形状对单粒子瞬态的影响在PMOS和NMOS器件中的不同机理,对单粒子瞬态加固设计具有指导性意义.     

0.13μm全耗尽绝缘体上硅晶体管单粒子效应仿真研究

利用计算机辅助设计Silvaco TCAD仿真工具,研究了0.13μm全耗尽绝缘体上硅(FD-SOI)晶体管单粒子瞬态效应,分析了不同线性能量转移(LET)、单粒子入射位置和工作偏置状态对单粒子瞬态的影响。结果表明,LET值的增加会影响沟道电流宽度,加大单粒子瞬态峰值及脉冲宽度。受入射位置的影响,由于栅极中央收集的电荷最多,FD-SOI器件的栅极中央附近区域单粒子瞬态效应最敏感。单粒子瞬态与器件工作偏置状态有很强的相关性,器件处于不同工作偏置状态下,关态偏置受单粒子效应影响最大,开态偏置具有最小的瞬态电流峰值和脉宽。     

反熔丝型FPGA单粒子效应及加固技术研究

在当今复杂电磁环境和强干扰的条件下,航空和航天装备的信号处理器件的逻辑可能产生意外翻转而产生功能失效,甚至导致系统工作状态异常,因此器件的可靠性至关重要.反熔丝型FPGA（现场可编程门阵列）因其低功耗、高可靠性、高保密性等特点,广泛应用于航空航天的电子系统中.文章在介绍反熔丝型FPGA的基本结构的基础上,对反熔丝型FPGA单粒子效应（SEE）进行了详细分析,提出了相应的SEE加固设计措施及实现方法.通过重离子地面加速试验对加固设计方法进行验证,试验结果及分析表明,加固设计方法可以有效提高商用现货（COTS）反熔丝型FPGA的可靠性,可以为同类型的电子系统设计提供有价值的参考.     

一种SRAM型FPGA单粒子效应故障注入方法

随着FPGA在航天领域的广泛应用,SRAM型FPGA的单粒子故障也越来越引起人们的重视,用故障注入技术模拟单粒子效应是研究单粒子效应对SRAM器件影响的重要手段,该文主要研究SRAM型FPGA单粒子翻转、单粒子瞬态脉冲的故障注入技术,并在伴随特性的基础上,提出一种单粒子瞬态脉冲故障注入技术。该方法使注入故障脉冲宽度达到...     

浮栅器件的单粒子翻转效应

基于中国原子能科学研究院的HI-13加速器,利用不同线性能量传输(LET)值的重离子束流对4款来自不同厂家的90 nm特征尺寸NOR型Flash存储器进行了重离子单粒子效应试验研究,对这些器件的单粒子翻转(SEU)效应进行了评估。试验中分别对这些器件进行了静态和动态测试,得到了它们在不同LET值下的SEU截面。结果表明高容量器件的SEU截面略大于低容量的器件;是否加偏置对器件的翻转截面几乎无影响;两款国产替代器件的SEU截面比国外商用器件高。国产替代器件SEU效应的LET阈值在12.9 MeV·cm²/mg附近,而国外商用器件SEU效应的LET阈值处于12.9~32.5 MeV·cm²/mg之间。此外,针对单粒子和总剂量效应对试验器件的协同作用也开展了试验研究,试验结果表明总剂量累积会增加Flash存储器的SEU效应敏感性,分析认为总剂量效应产生的电离作用导致了浮栅上结构中的电子丢失和晶体管阈值电压的漂移,在总剂量效应作用的基础上SEU更容易发生。     

Single Event Transient acquisition and mapping for space device Characterization

It is necessary for space applications to evaluate the sensitivity of electronic devices to radiations. It was demonstrated that radiations can cause different types of effects to the devices and possibly damage them [1] [2]. The interest in the effect of Single Event Transient (SET) has recently risen because of the increased ability of parasitic signals to propagate through advanced circuit with gate lengths shorter than 0.65 nm and to reach memory elements (in this case they become Single Event Upset (SEUs)). Analog devices are especially susceptible to perturbations by such events which can induce severe consequences, from simple artifacts up to the permanent fail of the device. This kinds of phenomena are very difficult to detect and to acquire, because they are not periodical. Furthermore, they can vary a lot depending on different parameters such as device technology and biasing. The main obstacle for the analysis is due to the maximum frequency of these signals, which is unknown. It is consequently difficult to set a correct sample frequency for the acquisition system. In this document a methodology to evaluate SETs in analog devices is presented. This method allows to acquire automatically these events and to easily study the sensitivity of the device by analyzing a “SETs cartography”. The advantages are different: it allows to easily acquire and analyze the SETs in an automatic way; the obtained results allow the user to accurately characterize the device under test; and, finally, the costs due to the implementation of the tests are lower than a classical analysis performed by a particle accelerator.     

基于锎源的N沟道VDMOS器件单粒子效应研究

分析了N沟道VDMOS器件的单粒子辐射损伤机理和损伤模式,讨论了VDMOS器件的单粒子辐射加固措施。使用锎源,对采取了加固措施的一款200 V高压N沟道VDMOS器件进行单粒子效应试验研究。对比分析了不同漏源电压和栅源电压以及不同真空度对VDMOS单粒子效应的影响,可为VDMOS器件的单粒子辐射加固、试验验证及应用提供参考。     

一种便携式VDMOS单粒子试验测试系统

设计了一种在线测试系统,用于监测垂直双扩散金属-氧化物半导体场效应晶体管(VDMOS)器件在单粒子试验中的单粒子效应。简述了实验原理,从偏置设计与波形获取及仪器控制与远程监测多个方面详细论述了测试系统的硬件结构;给出了软件的设计流程及测试系统的操作界面。最后应用该自动测试系统开展了试验,结果表面该系统稳定可靠,便携易用。     

A New Approach to Single Event Effect Tolerance Based on Asynchronous Circuit Technique

Some asynchronous circuit techniques are proposed to provide a new approach to Single Event Effect (SEE) tolerance in synchronous circuits. Two structures, Double Modular Redundancy (DMR) and Temporal Spatial Triple Modular Redundancy with Dual Clock Triggered Register (TSTMR-D), are presented. Three SEE tolerant 8051 cores with DMR, TSTMR-D and traditional Triple Modular Redundancy (TMR) are implemented in SMIC 0.35 μm process. The results of fault injection experiments indicate that DMR has a relatively low overhead on both area and latency than TMR, while tolerates SEU in sequential logic. TSTMR-D provides tolerance for both SEU and SET with reasonable area and latency overhead.     

微小卫星单粒子闩锁防护技术研究

对于在轨微小卫星而言,单粒子闩锁(Single Event Latchup,SEL)是最具破坏性的单粒子效应之一,其后果轻则损坏器件,重则使在轨卫星失效。首先介绍了SEL发生机理,分析并总结现有抗SEL的关键技术。其次提出了空间单粒子闩锁防护措施并设计了一种可恢复式抗SEL电源接口电路,实现对卫星星上设备的防闩锁及过流保护。最后利用脉冲激光模拟单粒子效应技术对具有飞行经验的芯片进行实验测试。实验结果表明,该电路能够准确地检测SEL的发生,有效解除SEL效应,保证系统运行稳定可靠。     

Single Event crosstalk shielding for CMOS logic

With advances in technology scaling, CMOS circuits are increasingly more sensitive to transient pulses caused by Single Event particles. Hardening techniques for CMOS combinational logic have been developed to address the problems associated with Single Event transients, but in these designs, Single Event crosstalk effects have been ignored. In order to complement the Single Event upset (SEU) hardening process, coupling effects among interconnects need to be considered in the Single Event hardening and analysis of CMOS logic gates due to technology scaling effects that increase both SE vulnerability and crosstalk effects. As technologies advance, the coupling effects increasingly cause SE transients to contaminate electronically unrelated circuit paths which can in turn increase the “Single Event susceptibility” of CMOS circuits. Serious effects may occur if the affected line is a clock line or an input line of voters in triple-modular redundancy (TMR) circuit. Hence, this work first analyzes Single Event crosstalk on recent technologies and then proposes hardening techniques to reduce Single Event crosstalk. Hardening results are demonstrated using HSpice Simulations with interconnect and device parameters derived in 90 nm technology.     

An alternative approach to measure alpha-particle-induced SEU cross-section for flip-chip packaged SRAM devices: High energy alpha backside irradiation

To evaluate a device sensitivity against alpha particles, traditional Single Event Effect (SEE) tests are conducted using isotope source, which emits particles just above 5 MeV. Relentless downscaling and higher packing density have driven the demand of developing increasingly complex packaging: smaller, thinner, having enormous input/output pins count per chip. Flip-chip bonded devices meet all these demands, but their testing against alpha particles is a big challenge. The range of alpha ions, emitted by the isotope sources, is very short, which precludes their penetration till active circuit – from either side of the chip. This paper presents an evidence that high energy alpha irradiation can potentially be used to measure and correlate alpha SEE cross-section for such devices. The proposed method uses high energy alpha particles, directed from the backside of die, to mimic low energy (~ 5 MeV) at the sensitive volume (SV). The incident particles penetrate the entire silicon substrate and deposit charge in the SV to induce upsets. The energy and LET of an ion at the SV, having traversed the entire substrate, is determined using TRIM. SEE experiments are performed on 14 nm FinFET SRAM devices, assembled in flip-chip and wire-bonded structures, respectively, for backside and traditional top-side testing. High energy alpha irradiations were simulated using CRÈME-MC – a Geant4 based Monte Carlo transport code. Tests and simulation results, for traditional and proposed methods, are presented for correlation.