金属互连线电迁移过程中的高温蠕变行为研究

基于ABAQUS有限元分析软件,对金属互连线的蠕变行为进行了研究,获取了高温下的蠕变应力分布云图,并分析了不同温度、不同升温速率等参数对铝硅合金互连线蠕变行为的影响规律。结果表明:在温度载荷作用下,铝硅合金互连线的蠕变应力在互连线狭窄部位即尺寸突变的部位,呈现明显的应力集中现象;随着温度载荷的升高,互连线内部的蠕变应力值逐渐增大,且二者之间的关系近似为一条直线;在其他条件均相同的情况下,升温速率越快,互连线内部应力达到最大值所用的时间就越短,导致互连线承受高应力值的时间就越长,从而会加速部件的失效。     

基于自动建模方法的互连可靠性分析

金属互连线中的电迁移现象是导致互连线失效的主要原因,影响电迁移(EM)的因素有温度、电流、材料特性和互连线的几何尺寸等。采用有限元分析方法,探究导致电迁移的这些因素的工作机制,以及这些机制之间的相互影响,并且采用原子通量散度(AFD)来衡量电迁移的大小。使用先进的自动建模并仿真的方法,得到互连线的材料属性、几何尺寸、电流密度,以及外界环境温度与AFD的关系,通过AFD的变化规律分析互连线的可靠性。结果表明,温度升高、电流增大、尺寸减小,都会降低互连线的可靠性。     

集成电路互连线电迁移测试方法与评价

介绍了研究集成电路互连线电迁移的两种方法：加速寿命试验和移动速度试验。对加速寿命试验进行了分析和评价。分析表明,加速寿命试验方法存在高应力条件与正常工作条件下互连线电迁移中金属离子扩散机制不同、BLACK方程的使用范围有限、受试件特殊结构影响和电阻温度系数TCR随温度变化等问题。介绍了一种改进方法。详细介绍了移动速度试验,指出了其在互连线电迁移研究中的应用。     

基于缺陷均匀分布的集成电路制造成品率与可靠性之间的关系模型

在集成电路可制造性设计研究中,成品率与可靠性之间的关系模型备受人们关注.缺陷对成品率和可靠性的影响不仅与出现在芯片上的缺陷粒径大小有关而且与缺陷出现在芯片上的位置有关.本文主要考虑了出现在互连线上的金属丢失物缺陷对互连线的影响,分析了同一粒径的缺陷出现在互连线不同位置对互连线有效宽度的影响,给出了基于缺陷均匀分布的互连线平均有效宽度,结合已有成品率和可靠性估计模型,提出了基于缺陷位置信息的集成电路制造成品率与可靠性之间的关系模型.在工艺线稳定的情况下,利用该工艺线的制造成品率可以通过该关系式有效地估计出产品的可靠性,从而有效地缩短新产品的研发周期.     

射频功率晶体管内匹配技术中键合线的建模仿真与参数提取

金属键合线互连是射频大功率晶体管内匹配技术中的关键手段.键合线的直径、长度、拱高和并列键合线间距等物　理参量,均对器件性能有很大影响.采用三维电磁仿真软件EMDS和射频电路设计软件ADS对金属键合线互连进行了建模　仿真和射频等效参数提取,分析了等效参数与键合线各物理参量之间的关系,针对具体的关系特点及内匹配技术中键合线...     

互连线和CMOS模型对性能影响的分析

在集成电路中,全局互连线的设计是关键.分析了互连线RC和RLC模型的不同特性;针对互连线与CMOS器件级联的电路进行分析.分析了集成电路中互连线和CMOS的模型对性能的影响,并给出了基于HSPICE软件的仿真结果.仿真结果表明,不同互连线和CMOS模型对系统传输特性有一定影响.     

键合线互连电路的优化设计

介绍了一种微波多芯片组件中芯片与传输线互连的键合线互连电路设计。采用低通滤波器方法设计的键合线互连电路结构,在键合线长度一定的情况下,能够显著提高键合线互连电路的频率响应。设计了一种基于3阶低通滤波器的键合线互连电路,将键合线的寄生电感融入了3阶低通滤波器中,改善了键合线互连电路的微波传输特性,提高了键合线互连电路的截止频率。采用微波电路设计软件和三维电磁场软件相结合的设计方法,对键合线互连电路的微波特性进行建模、分析,验证了这种电路设计方法的正确性。     

一种考虑温度时间-空间分布的解析互连延时模型

本文从热扩散方程出发,得到了互连温度时间-空间分布的解析表达式.考虑互连温度对互连电阻和Elmore延时的影响,同时提出了一种用以分析互连时间-空间温度分布效应对互连延时影响的等效内阻模型.基于所提出的模型,详细地分析了互连长度、输入信号频率和功率对互连延时的影响.所提出的互连温度分布和延时解析模型可以应用于深亚微米温度相关的互连性能分析中.     

具有高压互连线的多区双RESURF LDMOS击穿特性

对600V以上级具有高压互连线的多区双RESURF LDMOS击穿特性进行了实验研究,并对器件进行了二维、三维仿真分析.利用多区P-top降场层的结终端扩展作用以及圆形结构曲率效应的影响,增强具有高压互连线的横向高压器件漂移区耗尽,从而降低高压互连线对器件耐压的影响.实验与仿真结果表明,器件的击穿电压随着互连线宽度的减小而增加,并与P-top降场层浓度存在强的依赖关系,三维仿真结果与实验结果较吻合,而二维仿真并不能较好反映具有高压互连线的高压器件击穿特性.在不增加掩模版数、采用额外工艺步骤的条件下,具有30μm高压互连线宽度的多区双RESURF LDMOS击穿电压实验值为640V.所设计的高压互连器件结构可用于电平位移、高压结隔离终端,满足高压领域的电路设计需要.     

ULSI中铜互连线通孔电热性能的数值模拟

利用三维有限元模型对Cu互连线通孔进行了电流密度、温度和温度梯度的分布进行了模拟,比较了具有不同阻挡层材料的通孔内的电流密度、温度和温度梯度的分布.对于同一阻挡层材料,进行了不同通孔倾斜角的模拟.模拟结果指出,通过优化通孔倾斜角和优选阻挡层材料可有效地改善通孔内的电流密度和温度的分布,提高ULSI通孔互连的可靠性,这对通孔的设计提供了有益的参考.     

Propagation characteristics of high-Tc superconductinginterconnect for VLSI packaging predicted by a generalized two-fluidmodel

A generalized two-fluid model is used to analyze the propagation characteristics of high-Tc superconducting interconnects for very large scale integration (VLSI) packaging. The comparisons for surface impedance of YBa₂Cu₃O_7-x (YBCO) single crystals and thin films show data are in good agreement with the generalized two-fluid model. Based on the generalized two-fluid model, the temperature- and frequency-dependences of the attenuation constant are calculated, the transient responses of a pulse transmitted on a high-Tc superconducting interconnect are simulated, and a simple semi-empirical expression for rise time is given. The results based on the generalized two-fluid model predict an optimum operation temperature range for YBCO interconnect near at liquid nitrogen temperature     

基于DSP的嵌入式汉语文语转换系统及其VLSI设计方案

简要讨论了嵌入式文语转换(ETTS)系统的概念.介绍了一个基于DSP实时实现的嵌入式汉语文语转换(ECTTS)系统.基于DSP实现的结果,分析了ECTTS系统的VLSI实现方案,提出了基于动态内存管理的ECTTS系统前端处理VLSI实现方案,基于解码语音帧的ECTTS系统后端合成VLSI实现框架并对ECTTS系统的VLSI实现中的存储器及总线结构进行了讨论.     

Hybrid genetic-paired-permutation algorithm for improved VLSI placement

This paper addresses Very large-scale integration (VLSI) placement optimization, which is important because of the rapid development of VLSI design technologies. The goal of this study is to develop a hybrid algorithm for VLSI placement. The proposed algorithm includes a sequential combination of a genetic algorithm and an evolutionary algorithm. It is commonly known that local search algorithms, such as random forest, hill climbing, and variable neighborhoods, can be effectively applied to NP-hard problem-solving. They provide improved solutions, which are obtained after a global search. The scientific novelty of this research is based on the development of systems, principles, and methods for creating a hybrid (combined) placement algorithm. The principal difference in the proposed algorithm is that it obtains a set of alternative solutions in parallel and then selects the best one. Nonstandard genetic operators, based on problem knowledge, are used in the proposed algorithm. An investigational study shows an objective-function improvement of 13%. The time complexity of the hybrid placement algorithm is O(N²).     

超大规模集成电路中互连结构的逻辑模型

本文首次提出一种新观点，超大规模集成电路中互连结构的等效模型应具有层次性，对于底层的电路设计，应将互加看作一种具有分布参数的多端口网络，而对于高层次的模块设计，则应将互连看作一种逻辑元件，基于这种观点，本文提出了一种表格型的逻辑模型，它可以将互连产生的三种主要负效应：串扰、延迟和信号变形人武部考虑在内。     

An efficient multiple shortest augmenting paths algorithm for constructing high performance VLSI subarray

Reconfiguring a high-performance subarray of a VLSI array with faults is to construct a maximum target array with the minimum number of long interconnects, which can reduce communication costs, capacitance and dynamic energy dissipation. An existing work proved that the high performance VLSI subarray can be constructed in polynomial time using network flow algorithm. However, because of the disadvantage of the previous network model and the low-performing of standard network flow algorithms for reconfiguration, the efficiency of these algorithms is poor for constructing the high performance VLSI subarray. In this paper, we present an efficient multiple shortest augmenting paths algorithm for rapidly constructing high performance VLSI array. Firstly, we proposed an efficient data structure to construct the network model of the VLSI array with faults, which can dramatically reduce the size of the model compared with previous algorithm. Secondly, a multiple shortest augmenting path algorithm based on the new data structure is proposed, which can significant reduce the running time. Finally, we conduct solid experiments to highlight the efficiency of the proposed method in terms of the running time compared to the standard network flow algorithms. The experimental results show that on a 64 × 64 host array with 0.1% faults, the size of the network model can be reduced by about 50% and the average improvements in running time is up to 85.10% compared with four standard network flow algorithms.     

高温恒定电流电迁移可靠性试验及结果分析

介绍了评价电迁移可靠性的高温恒定电流试验方法,以电阻值超过初始值10％为失效判据,对某工艺的几组样品进行可靠性评价。该试验方法简便、可靠,适用于亚微米和深亚微米超大规模集成电路的可靠性评价。     

JPEG2000实时截断码率控制新算法及其VLSI结构设计

提出一种实时编码实时截断的码率控制算法.它根据已分解的小波子带内码块有效位平面数来预测未分解的小波子带内码块有效位平面数,并根据编码通道数和小波/量化权系数为当前编码码块分配码率.并提出一种JPEG2000编码实时截断,两级码率控制的编码体系结构.第一级采用本文提出的算法实时截断码流和编码通道.第二级在低码率下采用JPEG2000标准的PCRD优化算法搜索精确的分层截断点.在最优分层截断之前多数码流和编码通道被预先截断,存储器损耗小,实时性高.低码率下,图像质量跟JPEG2000标准一致.     

VLSI Implementation of a Neural Model Using Spikes

The paper presents a VLSI approach to approximate thereal-time dynamics of a neuron model inspired from the classicalmodel of Hodgkin and Huxley, in which analog inputs and outputsare represented by short spikes. Both the transient and the steady-statebehaviours of these circuits depend only on process-independentlocal ratios, thus enabling single or multiple-chip VLSI implementationsof very large analog neural networks in which parallelism, asynchronyand temporal interactions are kept as important neural processingfeatures. Measurements on an integrated CMOS prototype confirmexperimentally the expected electrical and temporal behavioursof the proposed neural circuits and illustrate some outstandingfunctional features of the neural model: spike-mediated modulationof the neural activity, self-regulation of the total activityin neural groups, and emulation of temporal interaction mechanismswith well controlled time constants at different scales.     

一种VLSI设计到赋权超图的转换系统

本文基于VLSI划分问题的需要,提出了一种VLSI设计到赋权超图转换算法.该算法解决的关键问题是,它读取和遍历Verilog语言描述的树状结构VLSI设计,将其转换为赋权超图并存储为指定的文件存储格式,从而有效地将VLSI划分问题转换为超图划分优化问题.进而,本文给出了VLSI设计到赋权超图的转换系统（VLSI/Hypergraph Converter,VHC）的处理流程图,并在Windows平台下用C＋＋设计实现了VHC系统.实验及分析表明,该系统能正确地将Verilog语言描述的门级CPU测试用例转换为赋权超图,避免了直接在VLSI线网上进行划分,提高了VLSI划分的效率.     

Top-down design of a VLSI digital filter bank

This paper relates theoretical investigations in digital signal processing (DSP) to the design of a VLSI digital filter bank (DFB). Emphasis is on a top-down approach to identify multilevel parallelisms inherent in a generic DSP algorithm and a new VLSI architecture. System level control and communication requirements are examined. Finite word length effects on filter accuracy are identified. The complexity of filter modules is reduced by partitioning large filter functions into a sum of smaller subfunctions. A memory intensive architecture minimizes design time. Up to 100 DRF modules are configured in parallel to perform signal processing up to 20 MHz. This VLSI DFB out performs sequential von Neumann architectures by several orders of magnitude using the same level of VLSI technology.