双逻辑低功耗运算电路设计分析

主要研究双逻辑低功耗运算电路设计,采用了函数逻辑立方体表示技术,进行了双模式的逻辑侦测与划分,并进行了RM逻辑面积优化。双逻辑低功耗运算电路设计是当前集成电路设计研究工作的重点内容,对降低运算电路功耗效果显著。     

SOC技术及系统级低功耗设计

介绍了SOC设计中的IP核可复用技术、软硬件协同设计技术、SOC验证技术、可测性设计技术以及低功耗设计技术。对SOC低功耗设计中的瞬态功耗优化、平均功耗优化以及功耗的物理来源、电容充放电功耗、短路功耗、静电漏电功耗进行了分析。并对典型SOC设计中采取降低芯片和封装电容、降低电源电压,达到降低功耗的技术进行了研究。最后对系统级功耗设计中的电源系统低功耗设计、工作系统低功耗设计进行了探讨。     

百万门级系统芯片低功耗技术研究

针对超大规模集成电路低功耗设计技术市场需求的迅速增大,提出了一种新的百万门级系统芯片低功耗设计流程,重点分析了芯片系统级、电路级、逻辑级与物理级四个不同的层次的低功耗设计方法,包括系统构架、时钟与功耗管理算法等低功耗关键技术。以某新型雷达SoC低功耗设计为例,采用SMIC 0.18 μm 1P6M CMOS工艺进行设计,版图尺寸为7.825 mm×7.820 mm,规模约为200万门。实验结果表明,在100 MHz工作频率下,采用新的低功耗设计流程后,前端设计阶段功耗降低了42.79%,后端设计阶段功耗降低了12.77%,芯片总功耗仅为350 mW。样品电路通过了用户某新型相控阵雷达系统的应用验证,满足小型化和低功耗的要求。     

基于功能仿真的RTL级低功耗优化

针对复杂集成电路设计中的功耗问题,提出了基于典型功能仿真和代码解析通过逻辑重组、操作隔离、预计算等技术实现寄存器传输级(RTL)低功耗的优化方法,该方法工作在RTL级,只需得到HDL仿真工具的支持。实验结果表明采用文章所提出的优化方法可显著降低电路功耗。     

在线座谈

在线注册:http:www.ECCN.com/reg本次研讨会将对关注功耗的设计方法做一个比较全面的介绍,以Actel的最低功耗FPGA IGLOO为例,系统的介绍功耗的来源和影响功耗的各种因素,以及在开始一个设计的时候,设计者如何选择低功耗器件,设计的时候用来降低静态功耗和动态功耗的方法。参加本讲座以后,能够对如何为一个低功耗设计选择器件,以及如何在设计的时候降低功耗有所了解。     

IGLOO PLUS入门级工具套件

低成本IGLOO PLUS入门级工具套件备有IGLOO PLUS系列低功耗现场可编程门阵列,提供可编程逻辑器件极佳的每I／O功耗、逻辑和功能比率。IGLOOPLUS入门级工具套件可让设计人员快速评测Actel的IGLOOPLUS系列器件,并构建其设计原型。IGLOOPLUS器件的系统门范围为30000-125000个,电压范围为1．2-1．5V,     

采用FPGA的低功耗系统设计

结合采用低功耗元件和低功耗设计技术在目前比以往任何时候都更有价值.随着元件集成更多功能,并越来越小型化,对低功耗的要求持续增长.当把可编程逻辑器件用于低功耗应用时,限制设计的低功耗非常重要.本文将讨论减小动态和静态功耗的各种方法,并且给出一些例子说明如何使功耗最小化.     

低功耗超快速CPLD

最低的动态功耗与超快速的性能传统上，对于有限供电电源的场合，电路设计者在用CPLD(复杂可编程逻辑器件)设计和实现数字电子系统时，最基本的也是最关心的是如何达到低功耗。高性能的计算和通信系统常常有相对较高的功耗，而设计者考虑的是如何以低功耗去降低运作成本，同时又能增强系统的可靠性。CPLD的功耗包括静态功耗和动态功耗。因此，选择低功耗的CPLD器件至关重要。Lattice公司推出的ispMACH4000系列器件以低动态功耗实现在业界领先的速度性能，同时支持界在3.3V与2.5V之间的I/O标准。通过使用0.18mm的电可擦除(E2CMOS)…     

SOC时代低功耗设计的研究与进展

在片上系统(SOC)时代,芯片内核的超高功耗密度以及移动应用市场对低功耗的无止境需求,使低功耗设计变得日益重要.文章全面系统地介绍了低功耗设计的相关内容,包括背景、原理和不同层次的功耗优化技术,着重介绍了面向SOC的系统级功耗优化技术.通过对已有研究成果按设计抽象层次和系统功能的分析,指出了其优化的全局性不够充分.提出了基于软硬件协同设计的系统功耗优化思路和设计流程,展望了SOC低功耗设计的发展方向.     

低功耗千兆光互连链路的研制

基于可编程门阵列(FPGA)器件实现了低功耗的高速光互连链路。采用电时分复用(ETDM)技术在1根光纤上实现了G,数据信号的虚拟并行传输,降低了系统成本。链路物理层带宽达1056Mbit／s,链路稳定传输带宽为545Mbit／s,在应用层可得到300Mbit／s的数据传输率。并通过合理的器件选择、动态功耗管理和低功耗编码等设计方法,使系统功耗降低50％。     

基于PLC和LLC的充电桩电源模块设计

本文研究了电动汽车直流充电桩电源技术,针对电网谐波污染和传统AC-DC转换电路硬开关损耗大的问题,提出了以PFC+LLC结构作为直流充电桩电源模块。该结构的初级PFC可以使输入电流为正弦波,减小电网的谐波污染;次级LLC谐振电路工作在软开关状态,减少了开关损耗。测试结果表明PFC电路可以将输入电流变为正弦,减少谐波污染;LLC电路可以工作在软开关状态下,开关损耗低,整机效率达到88%。     

Design of on-chip 15-18 GHz ultra low noise amplifier

With rapid development communication system, high signal to noise ratio （SNR） system is required. In high frequency bandwidth, high loss, low Q inductors and high noise figure is a significant challenge with on-chip monolithic microwave integrated circuits （MMICs）. To overcome this problem, high Q, low loss transmission line characteristics was analyzed. Compared with the same inductor value of the lumped component and the transmission line, it has a higher Q value and lower loss performance in high frequency, and a 2-stage common-source low noise amplifier （LNA） was presented, which employs source inductor feedback technology and high Q low loss transmission line matching network technique with over 17.6 dB small signal gain and 1.1 dB noise figure in 15 GHz-18 GHz. The LNA was fabricated by WIN semiconductors company 0.15 μm gallium arsenide （GaAs） P high electron mobility transistor （P-HEMT） process. The total Current is 15 mA, while the DC power consumption is only 45 mW.     

开关磁阻电机功率变换器杂散参数抑制及散热设计

功率变换器是开关磁阻电机调速系统(以下简称SRD)中保证电机可靠稳定运行的关键部件。在大功率功率变换器设计过程中,对电路的杂散参数以及功率器件的散热等问题的处理是功率变换器结构设计的关键。针对电路中的杂散参数,本文在设计功率变换器过程中构建了60KW开关磁阻电机功率变换器逆变回路杂散电感等效分布模型,分析了杂散电感在器件关断过程中的影响。在此基础上,引入低感叠层母线技术,从结构设计与工程运用角度出发对该母线进行分析,理论计算与仿真结果均表明设计方案比传统设计方案更有效地抑制了主回路杂散电感值。针对功率器件的散热问题,提出一种针对SRM负载的功率电路热损耗估算方法。通过损耗计算得出功率变换器主电路中损耗的来源和器件温升变化,对功率变换器的进一步设计改进有重要意义。     

Integrated laser Mach-Zehnder modulator on indium phosphide free ofmodulated-feedback

The main problem of integrated laser/Mach-Zehnder modulators is the modulated feedback due to reflections on the output multimode image (MMI). We have solved this problem changing the modulator technology from "deep-ridge" to "shallow-ridge" technology. In that case, the index step seen by the light in the MMI is far lower, then reflections which are nondetectable in optical low coherence reflectometry (OLCR) and there is no laser resonance left. This technology also enables a wider bandwidth (thanks to a stronger electrooptic effect) and a higher output power (better coupling between laser and modulator and lower loss of shallow-ridge guides)     

Energy-efficient Hardware Architecture and VLSI Implementation of a Polyphase Channelizer with Applications to Subband Adaptive Filtering

Polyphase channelizer is an important component of subband adaptive filtering systems. This paper presents an energy-efficient hardware architecture and VLSI implementation of polyphase channelizer, integrating algorithmic, architectural and circuit level design techniques. At algorithm level, low complexity polyphase channelizer architecture is derived using multirate signal processing approach. To reduce the computational complexity in polyphase filters, computation sharing differential coefficient (CSDC) method is effectively used as an architectural level technique. The main idea of CSDC is to combine the strength of augmented differential coefficient method and subexpression sharing. Efficient circuit-level techniques: low power commutator implementation, dual-VDD scheme and novel level-converting flip-flop (LCFF), are also used to further reduce the power dissipation. The proposed polyphase channelizer consumes 352 mW power with throughput of 480 million samples per second (MSPS). A test chip has been fabricated in 0.18 μm CMOS technology and its functionality is verified. Chip measurement results show that the dual-VDD implementation achieves a total power saving of 2.7 X.     

简洁构型与馈电的宽带双极化金属锥阵列天线北大核心CSCD

本文提出了一种宽带双极化金属锥阵列天线。该阵列天线以传统的旋转体天线结构为主体,通过在锥体底部开设四道正交的直通槽,以便在锥状单元内部形成可与地板间构成匹配谐振腔的开放式空腔结构。在阵列中,任意两个相邻的锥状单元之间可形成类似于Vivaldi天线的辐射缝隙结构。馈电采用同轴馈电方式,探针无弯折结构,金属锥体无弯折过孔。每个金属锥状单元独立,可极大简化加工、装配和维护过程。该天线具有两个正交极化,分别由左右和前后相邻单元构成。仿真结果表明,在频率范围为2～8GHz内,阵列大部分有源VSWR小于2,小部分端口有源VSWR小于2.5 (相对带宽为120%)。     

（英）亚毫米波波段波束功率合成方法

对于亚毫米波或太赫兹系统而言,关键问题是功率源的输出功率非常小。 功率合成技术是增加输出功率的有效方法。 然而,在微波和毫米波段中使用的常规功率合成方法（例如电路级合成或波导内空间合成）在亚毫米波波段因损耗高及难以加工等因素而受到制约。 本文提出了一种基于准光学技术的波束功率合成方法。 它具有损耗低,合成效率高,相对容易制造的优点。本文给出了分析,仿真和实验结果,并得到高的输出合成效率。     

基于S曲线全局动态调光的改进算法

S曲线全局动态调光算法可以降低LED液晶显示器的功耗,同时能够提高显示图像的静态对比度,但该算法会造成部分图像色彩失真和细节丢失。针对这一问题,本文提出一种图像细节层分离与视觉显著性理论相结合的S曲线改进算法。首先,将原始图像转换至HSV色彩空间进行亮度和色度分离;然后,在图像亮度分量上采用双边滤波得到图像的基础层与细节层,基础层采用S曲线进行动态范围拉伸,实现像素补偿,细节层则运用视觉显著性理论进行分区与权值增强,弥补由像素补偿带来的细节损失;最后,将处理后的各层图像转换至RGB空间显示。将本文算法的仿真结果与原S曲线算法的结果进行对比。结果显示,本文算法在维持原算法功耗降低和静态对比度提升水平不变的基础上,解决了原算法在部分图像中出现的色彩失真和细节丢失问题,提升了图像的视觉显示效果,同时本文算法的仿真结果具有更大的信息熵和平均梯度。     

UWB radio module design for wireless sensor networks

In this paper, we describe an impulse-based ultra wideband (UWB) radio system for wireless sensor network (WSN) applications. Different architectures have been studied for base station and sensor nodes. The base station node uses coherent UWB architecture because of the high performance and good sensitivity requirements. However, to meet complexity, power and cost constraints, the sensor module uses a novel non-coherent architecture that can autonomously detect the UWB signals. The radio modules include a transceiver block, a baseband processing unit and a power management block. The transceiver block includes a Gaussian pulse generator, a multiplier, an integrator and timing circuits. For long range applications, a wideband low noise amplifier (LNA) is included in the transceiver of the sensor module, whereas in short range applications it is simply eliminated to further reduce the power consumption. In order to verify the proposed system concept, circuit level implementation is studied using 1.5 V 0.18 μm CMOS technology. Finally, the UWB radio modules have been designed for implementation in liquid-crystal-polymer (LCP) based System-on-Package (SoP) technology for low power, low cost and small size integration. A small low cost, double-slotted, Knight’s helm antenna is embedded in the LCP substrate, which shows stable characterization and a return loss better than ?10 dB over the UWB band.     

System-level power consumption modeling and tradeoff analysistechniques for superscalar processor design

This paper presents systematic techniques to find low-power high-performance superscalar processors tailored to specific user applications. The model of power is novel because it separates power into architectural and technology components. The architectural component is found via trace-driven simulation, which also produces performance estimates. An example technology model is presented that estimates the technology component, along with critical delay time and real estate usage. This model is based on case studies of actual designs. It is used to solve an important problem: decreasing power consumption in a superscalar processor without greatly impacting performance. Results are presented from runs using simulated annealing to reduce power consumption subject to performance reduction bounds. The major contributions of this paper are the separation of architectural and technology components of dynamic power the use of trace-driven simulation for architectural power measurement, and the use of a near-optimal search to tailor a processor design to a benchmark