一种带有精准调谐结构的有源RC低通滤波器的设计

提出了一种带有精准调谐结构的有源RC低通滤波器的设计方案,其截止频率为5MHz,并在0.18μm标准CMOS工艺线上流片得到验证.调谐精度达到（-1.24%, +2.16%) ,测试中得到验证.调谐系统所占芯片面积仅为主滤波器面积的1/4.调谐系统完成调谐功能后会自动关闭,降低了功耗以及对主滤波器的串扰.以50Ω作为源阻抗,滤波器带内3阶交调量（IIP3）好于16.1dBm.滤波器输入参考噪声为36μVrms.滤波器群延迟时间波动测试结果为24ns.滤波器功耗为3.6mW.带有这种调谐结构的滤波器容易被实现,可以用于很多无线低中频应用中,例如全球定位系统、全球通和码分多址等芯片系统中.     

一种带有片上电荷泵自动调谐结构的非对称带通滤波器的设计

摘要：提出了一种采用片上电荷泵自动调谐结构的MOSFET-C非对称带通滤波器的设计方案,并在UMC（联合电子公司）0.18um标准CMOS工艺线上流片得到验证。带有调谐系统的滤波器采用主从技术进行连续调谐,完成调谐功能后电荷泵输出调谐电压为2.663V,远高于电源电压,提高了滤波器的线性度。非对称带通滤波器带宽为（2.73MHz,5.34MHz）且具有3阶低通和2阶高通特性。以50欧姆作为源阻抗,滤波器带内3阶交调量（IIP3）为16.621dBm。输入参考噪声为47.455uVrms。在1.8V电源电压下,主滤波器功耗为3.528mW,自动调谐电路功耗为2.412mW。带有自动调谐系统的滤波器整个系统占芯片面积0.592mm2,可用于无线局域网,全球定位和蓝牙等系统中。     

一种用于WLAN收发器带有自动调谐系统的低功耗Gm-C滤波器

本文用0.35um CMOS工艺实现了一个用于WLAN收发器的六阶连续调谐巴特沃斯Gm-C低通滤波器。滤波器设计中采用了内部节点压缩技术来提高动态范围,还对滤波器的部分结构进行了有效的优化,极大地减小芯片的功耗和面积。测试结果显示滤波器的动态范围为77.5dB,群延时波纹小于16.3ns,截止频率精确度在3%以内,滤波器的带内三阶交调量（IIP3）为0dBm。在电源电压2.85V时,包括调谐电路在内的整个滤波器消耗电流仅为1.42mA（5MHz的截止频率）或2.81mA(10MHz的截止频率),而且版图面积仅为0.175mm2.     

一种适用于多波段无线通信的品质因数增强型的CMOS射频滤波器

提出了一种使用品质因数增强型的有源电感的射频带通滤波器,描述了在宽射频频段上可调谐的品质因数增强型的有源电感设计技术,而且解释了与有源电感噪声和稳定性相关的问题.该滤波器采用0.18μm CMOS工艺制造,它所占用芯片的有效面积仅为150μm×200μm.测试结果表明:该射频滤波器中心频率为2.44GHz时,3dB带宽为60MHz,中心频率可在2.07～2.44GHz范围内调谐,1dB压缩点为-15dBm,而静态功耗为10.8mW;在中心频率为2.07GHz时,滤波器的品质因数可达到103.     

一种适用于多波段无线通信的品质因数增强型的CMOS射频滤波器

提出了一种使用品质因数增强型的有源电感的射频带通滤波器,描述了在宽射频频段上可调谐的品质因数增强型的有源电感设计技术,而且解释了与有源电感噪声和稳定性相关的问题.该滤波器采用0.18μm CMOS工艺制造,它所占用芯片的有效面积仅为150μm×200μm.测试结果表明:该射频滤波器中心频率为2.44GHz时,3dB带宽为60MHz,中心频率可在2.07～2.44GHz范围内调谐,1dB压缩点为-15dBm,而静态功耗为10.8mW;在中心频率为2.07GHz时,滤波器的品质因数可达到103.     

一种带有精确调谐系统的多标准有源RC滤波器

本文介绍了一种低功耗、高线性度、多标准有源RC滤波器,此滤波器带有设计巧妙而精确的调谐系统。该滤波器使用在IEEE 802.11a/b/g (9.5MHz) 和 DVB-H (3MHz, 4MHz)系统中。滤波器使用数字控制多晶硅电阻阵列和锁相环技术的调谐系统,它提供了4%以内的调谐精度。为了节约功耗和减小数字信号的干扰,它在调谐之后可以自动关闭。滤波器带外3阶交调量26dBm。群延时差值为50ns。接收和发送滤波器分别消耗3.4mA和2.3mA, 电源电压为2.85V,调谐系统消耗2mA。此电路采用0.35微米、47GHz锗硅BiCMOS工艺。接收滤波器和发送滤波器的面积（除去校正系统）为0.21-mm2和0.11-mm2。     

一种应用于低中频接收机的复数滤波器

基于SMIC 0.18 μm 1P4M CMOS工艺,实现了一种2阶复数滤波器。该滤波器的中心频率为-1 MHz,带宽为1 MHz,可以实现10 dB的镜像抑制比。采用Tow-Thomas结构,可以灵活调节滤波器的增益和频率,并减小滤波器对寄生参数的敏感程度。采用基于张弛振荡器的频率调谐电路,简化了调谐电路,同时节约了芯片面积和功耗。流片测试结果显示,该滤波器的面积为0.78 mm²,电源电流为1.28 mA。     

低功耗跨导-电容滤波器及其调谐电路的设计

设计了一种以Nauta跨导为单元结构的5阶切比雪夫跨导-电容带通滤波器及其调谐电路.该电路应用于低中频结构的北斗卫星导航接收机射频前端.滤波器的中心频率为4.092MHz,带宽设计为±2.046 MHz.该滤波器采用锁相环结构的片上自动频率调谐电路,用TSMC0.13 μm RF CMOS工艺实现,芯片面积仅为0.24 mm2,可以在低电压下工作,电路总功耗仅为1.68 mW.     

应用于直接变频结构中的高线性度低功耗CMMB调谐器的基带电路

本文用0.35微米锗硅BiCMOS工艺设计了用于中国多媒体移动电视的模拟基带电路,此接收机芯片采用直接下变频结构。此基带电路使用了带有精确调谐系统的高线形度8阶切比雪夫低通滤波器,测试结果表明此滤波器有0.5dB的带内纹波,带宽调谐系统的误差在4%以内。在截止频率为4MHz的情况下对6MHz的信号有35dB的衰减。基带部分使用抽电流型的可变增益放大器,提供至少40dB的增益,并且带有出色的温度补偿。此基带电路的带外三阶交调量（OIP3）为25.5dBm,电源电压2.8V,总电流为16.4mA,芯片面积为1.1mm2。     

新型双声道音频Σ-ΔDAC小面积插值滤波器的设计实现

该文提出了一种新型双声道音频Σ-Δ数模转换器(DAC)小面积插值滤波器设计方法。该方法采用左右两个声道复用一个插值滤波器的新型结构,并利用存储器实现第1级半带滤波器,从而降低芯片的实现面积。提出重新排序方法,保证复用后两个声道的同步。设计在TSMC 0.18μm 1.8 V/3.3 V 1P5M CMOS工艺上实现,测试信噪比为106 dB,数字部分芯片的面积仅为0.198 mm2,功耗为0.65 mW。这种设计方法降低了Σ-ΔDAC系统中数字部分的面积和功耗,给模拟部分留有较大的设计裕量,这对模数混合系统的设计具有重要的意义。     

A widely tunable continuous-time LPF for a direct conversion DBS tuner

A continuous-time 7th-order Butterworth Gm-C low pass filter (LPF) with on-chip automatic tuning circuit has been implemented for a direct conversion DBS tuner in 0.35μm SiGe BiCMOS technology. The filter's -3 dB cutoff frequency f0 can be tuned from 4 to 40 MHz. A novel on-chip automatic tuning scheme has been successfully realized to tune and lock the filter's cutoff frequency. Measurement results show that the filter has -0.5 dB passband gain, +/- 5% bandwidth accuracy, 30 nV/Hz1/2 input referred noise, -3 dBVrms passband IIP3, and 27 dBVrms stopband IIP3. The I/Q LPFs with the tuning circuit draw 13 mA (with f0 = 20 MHz) from 5 V supply, and occupy 0.5 mm2.     

GPS接收机镜像信号抑制

分析了GPS接收机镜像信号抑制的要求,设计应用于低中频GPS接收机的镜像抑制复数滤波器.滤波器基于OTA-C双二次结构,通过线性变换实现频率搬移.采用了带源极负反馈的全差分跨导器以扩大输入线性范围.设计了基于环形振荡器的数字调谐锁相环以减小滤波器频率偏差.电路采用0.18μm CMOS工艺实现.测试结果表明,滤波器带宽为3.1MHz,偏移5MHz抑制为50dB,频率修调误差小于±1.5%.镜像抑制大于35dB.1.8V电源电压下滤波器和修正电路电流分别为0.82mA和0.23mA.     

A 4th-order reconfigurable analog baseband filter for software-defined radio applications

This paper presents a 4th-order reconfigurable analog baseband filter for software-defined radios.The design exploits an active-RC low pass filter（LPF） structure with digital assistant,which is flexible for tunability of filter characteristics,such as cut-off frequency,selectivity,type,noise,gain and power.A novel reconfigurable operational amplifier is proposed to realize the optimization of noise and scalability of power dissipation.The chip was fabricated in an SMIC 0.13μm CMOS process.The main filter and frequency calibration circuit occupy 1.8×0.8 mm² and 0.48×0.25 mm² areas,respectively.The measurement results indicate that the filter provides Butterworth and Chebyshev responses with a wide frequency tuning range from 280 kHz to 15 MHz and a gain range from 0 to 18 dB.An IIP3 of 29 dBm is achieved under a 1.2 V power supply.The input inferred noise density varies from 41 to 133 nV/（Hz）^1/2 according to a given standard,and the power consumptions are 5.46 mW for low band（from 280 kHz to 3 MHz） and 8.74 mW for high band（from 3 to 15 MHz） mode.     

A dual-mode complex filter for GNSS receivers with frequency tuning

A fifth/seventh order dual-mode OTA-C complex filter for global navigation satellite system receivers is implemented in a 0.18 fxm CMOS process. This filter can be configured as the narrow mode of a 4.4 MHz bandwidth center at 4.1 MHz or the wide mode of a 22 MHz bandwidth center at 15.42 MHz. A fully differential OTA with source degeneration is used to provide sufficient linearity. Furthermore, a ring CCO based frequency tuning scheme is proposed to reduce frequency variation. The measured results show that in narrow-band mode the image rejection ratio (IMRR) is 35 dB, the filter dissipates 0.8 mA from the 1.8 V power supply, and the out-of-band rejection is 50 dB at 6 MHz offset. In wide-band mode, IMRR is 28 dB and the filter dissipates 3.2 mA. The frequency tuning error is less than ±2%.     

A 60-mW 200-MHz continuous-time seventh-order linear phase filter with on-chip automatic tuning system

A full CMOS seventh-order linear phase filter based on g/sub m/-C biquads with a -3-dB frequency of 200 MHz is realized in 0.35-/spl mu/m CMOS process. The linear operational transconductance amplifier is based on complementary differential pairs in order to achieve both low-distortion figures and high-frequency operation. The common-mode feedback (CMFB) employed takes advantage of the filter architecture; incorporating the load capacitors into the CMFB loop improves further its phase margin. A very simple automatic tuning system corrects the filter deviations due to process parameter tolerances and temperature variations. The group delay ripple is less than 5% for frequencies up to 300 MHz, while the power consumption is 60 mW. The third-harmonic distortion is less than -44 dB for input signals up to 500 mV/sub pp/. The filter active area is only 900 /spl times/ 200 /spl mu/m/sup 2/. The supply voltages used are /spl plusmn/1.5 V.     

低功耗Zigbee收发器镜像抑制滤波器设计

分析镜像抑制和带外衰减的要求,设计了适用于2.4 GHz Zigbee无线收发前端的镜像抑制滤波器.电路采用7阶巴特沃思OTA-C双二次结构.通过线性变换实现复数滤波.采用交叉耦合输入跨导器,扩大了输入线性范围.为减小滤波器频率偏差,设计了一种锁相环频率修调电路.电路利用0.18 μm CMOS工艺实现.测试结果表明,复数滤波器带宽2.54MHz,镜像抑制大于35 dB,偏移3.5 MHz抑制超过50 dB.在1.8 V电源电压下电流为0.86 mA.     

A reconfigurable OTA-C baseband filter with wide digital tuning for GNSS receivers

The design of a digitally-tunable sixth-order reconfigurable OTA-C filter in a 0.18-μm RFCMOS process is proposed.The filter can be configured as a complex band pass filter or two real low pass filters.An improved digital automatic frequency tuning scheme based on the voltage controlled oscillator technique is adopted to compensate for process variations.An extended tuning range(above 8:1) is obtained by using widely continuously tunable transconductors based on digital techniques.In the complex band pas...     

A 2.4 GHz 6.6 mA fully differential CMOS PLL frequency synthesiser

A 2.4 GHz 6.6 mA fully differential CMOS phase-locked loop (PLL) frequency synthesiser with an on-chip capacitance-calibrated loop filter is presented. The frequency synthesiser includes a differential-tuning voltage-control oscillator (VCO) and a fully differential charge-pump (CP) to reject the common-mode noise. A combination of analogue tuning and digital tuning techniques (4-bit binary weighted capacitor array) is utilised to extend the tuning range of the VCO. A novel topology and an optimisation strategy are utilised to reduce the power consumption of the frequency divider. The capacitance in the loop filter is on-chip calibrated so that the loop dynamic characteristics are accurately controlled despite the process variation. The frequency synthesiser has been implemented in UMC 0.18 μm CMOS. The measured results show that the VCO achieves a 29% tuning range, from 2.056 to 2.758 GHz. The phase noise of the frequency synthesiser is ? 117.2 dBc/Hz at 1 MHz frequency offset from the 2.3 GHz carrier. The settling time is less than 50 μs, and the capacitance in the loop filter could be on-chip calibrated to ±3.9% precision. The whole frequency synthesiser only consumes 6.6 mA current from a 1.8 V power supply.     

A Wide Tuning Range Gm –C Continuous-Time Analog Filter

A CMOS operational transconductance amplifier (OTA) for low-power and wide tuning range filter application is proposed in this paper. The OTA can work from the weak inversion region to the strong inversion region to maximize the transconductance tuning range. The transconductance can be tuned by changing its bias current. A fifth-order Elliptic low-pass filter implemented with the OTAs was integrated by TSMC 0.18-mum CMOS process. The filter can operate with the cutoff frequency of 250 Hz to 1 MHz. The wide tuning range filter would be suitable for multi-mode applications, especially under the consideration of saving chip areas. The third-order inter-modulation (IM3) of -40 dB was measured over the tuning range with two tone input signals. The power consumption is 0.8 mW at 1-MHz cutoff frequency and 1.8-V supply voltage with the active area less than 0.3 mm²     

Design of low-voltage CMOS continuous-time filter with on-chipautomatic tuning

A technique for designing a low-voltage continuous-time active filter is presented in this paper. In this technique, current sources are added to the inverting or noninverting op-amp terminals such that the op-amp input common-mode voltages can be set close to one of the supply rails to allow low-voltage operation. An automatic frequency and Q tuning technique is proposed for tuning the active filter using programmable capacitor arrays (PCAs). The proposed tuning technique does not require any peak detectors, which are difficult to implement at a low supply voltage. Instead, it uses a few analog comparators, a digital comparator, and a few binary counters to adjust the PCAs. To demonstrate the proposed techniques, a 1-V 1-MHz second-order filter fabricated in a conventional 1.2-μm CMOS process is presented. For a 5-kHz input signal, the filter achieves a THD of -60.2 dB for a peak-to-peak output voltage of 600 mV. The frequency tuning range is between 585 kHz and 1.325 MHz. The measured power consumption for the filter alone consumes about 0.52 mW and for the entire system consumes about 1.6 mW for a supply voltage of ±0.5 V