A low power direct conversion receiver RF front-end with high in-band IIP2/IIP3 and low 1/f noise

A low power direct-conversion receiver RF front-end with high in-band IIP2/IIP3 and low 1/f noise is presented. The front-end includes the differential low noise amplifier, the down-conversion mixer, the LO buffer, the IF buffer and the bandgap reference. A modified common source topology is used as the input stages of the down-conversion mixer (and the LNA) to improve IIP2 of the receiver RF front-end while maintaining high IIP3. A shunt LC network is inserted into the common-source node of the switching pairs in the down-conversion mixer to absorb the parasitic capacitance and thus improve IIP2 and lower down the 1/f noise of the down-conversion mixer. The direct-conversion receiver RF front-end has been implemented in 0.18 μm CMOS process. The measured results show that the 2 GHz receiver RF front-end achieves +33 dBm in-band IIP2, 21 dB power gain, 6.2 dB NF and −2.3 dBm in-band IIP3 while only drawing 6.7 mA current from a 1.8 V power supply.     

A 60-GHz Phased Array Receiver Front-End in 0.13-$mu {hbox{m}}$ CMOS Technology

This paper presents a fully integrated dual-antenna phased-array RF front-end receiver architecture for 60-GHz broadband wireless applications. It contains two differential receiver chains, each receiver path consists of an on-chip balun, ag_m-boosted current-reuse low-noise amplifier (LNA), a sub-harmonic dual-gate down-conversion mixer, an IF mixer, and a baseband gain stage. An active all-pass filter is employed to adjust the phase shift of each LO signal. Associated with the proposed dual conversion topology, the phase shift of the LO signal can be scaled to one-third. Differential circuitry is adopted to achieve good common-mode rejection. The g_m-boosted current-reuse differential LNA mitigates the noise, gain, robustness, stability, and integration challenges. The sub-harmonic dual-gate down-conversion mixer prevents the third harmonic issue in LO as well. Realized in a 0.13-mum 1P8M RF CMOS technology, the chip occupies an active area of 1.1 times 1.2 mm². The measured conversion gain and input P1 dB of the single receiver path are 30 dB and -27 dBm , respectively. The measured noise figure at 100 MHz baseband output is around 10 dB. The measured phased array in the receiver achieves a total gain of 34.5 dB and theoretically improves the receiver SNR by 4.5 dB. The proposed 60 GHz receiver dissipates 44 mW from a 1.2 V supply voltage. The whole two-channel receiver, including the vector modulator circuits for built-in testing, consumes 93 mW from a 1.2 V supply voltage.     

A 23–37 GHz Miniature MMIC Subharmonic Mixer

A novel configuration of subharmonic mixer using an anti-parallel diode pair is presented for operating over the 23-37 GHz band. The monolithic microwave integrated circuit is implemented by GaAs 0.15 mum PHEMT technology with the compact size of 0.85 times 0.85 mm². This mixer employs a directional coupler, LC low-pass filter, and a short stub for isolating three ports corresponding to radio frequency (RF), local oscillation (LO) input, and intermediate frequency (IF) output ports. The directional coupler also provides impedance transformation between the diode pair, RF, and LO ports. This makes the subharmonic mixer more compact and flexible. The best conversion loss of the subharmonic mixer is 9.4 dB, and the LO-to-RF and LO-to-IF isolations are better than 22 and 31 dB, respectively.     

An I/Q mixer with an integrated differential quadrature all-pass filter for on-chip quadrature LO signal generation

A down-conversion in-phase/quadrature (I/Q) mixer employing a folded-type topology, integrated with a passive differential quadrature all-pass filter (D-QAF), in order to realize the final down-conversion stage of a 60 GHz receiver architecture is presented in this work. Instead of employing conventional quadrature generation techniques such as a polyphase filter or a frequency divider for the local oscillator (LO) of the mixer, a passive D-QAF structure is employed. Fabricated in a 65 nm CMOS process, the mixer exhibits a voltage gain of 7-8 dB in an intermediate frequency (IF) band ranging from 10 MHz-1.75 GHz. A fixed LO frequency of 12 GHz is used to down-convert a radio frequency (RF) band of 10.25-13.75 GHz. The mixer displays a third order input referred intercept point (IIP₃) ranging from -8.75 to -7.37 dBm for a fixed IF frequency of 10 MHz and a minimum single-sideband noise figure (SSB-NF) of 11.3 dB. The mixer draws a current of 6 mA from a 1.2 V supply voltage dissipating a power of 7.2 mW.     

A 1.57-GHz RF front-end for triple conversion GPS receiver

A low-power, 1.57 GHz RF front-end for a Global Positioning System (GPS) receiver has been designed in a 1.0 μm BiCMOS technology. It consists of a low noise amplifier with 15 dB of gain, a single balanced mixer with 6.3 mS of conversion g_m, a Colpitts LC local oscillator, and an emitter coupled logic (ECL) divide-by-eight prescaler. This front-end has a single sideband (SSB) noise figure of 8.1 dB and is part of a triple conversion superheterodyne receiver whose IF frequencies are 179, 4.7, and 1.05 MHz. Low power consumption has been achieved, with 10.5 mA at 3 V supply voltage for the front-end, while the complete receiver is expected to draw about 12 mA     

A 170 MHz RF front-end for ERMES pager applications

A 170 MHz RF front-end for ERMES pager applications has been implemented in a 1.2 μm BiCMOS technology. The chip comprises a low noise amplifier with AGC, a double balanced mixer, a varactor tuned LC local oscillator, and an IF strip containing an AGC amplifier and a double balanced mixer with integrated active output filter. The LNA has a measured gain of 22.3 dB at 170 MHz with a usable AGC range of approximately 20 dB while the conversion transconductance of the mixer is 130 μS. This front-end is suitable for direct conversion and superheterodyne pager receivers, and its noise figure is 6.2 dB. Low power operation has been achieved with the front-end drawing 230 μA at 3 V, which is compatible with the intended application in wrist-watch style pagers     

Broadband single- and double-balanced resistive HEMT monolithicmixers

A double-balanced (DB) 3-18 GHz and a single-balanced (SB) 2-16 GHz resistive HEMT monolithic mixer have been successfully developed. The DB mixer consists of a AlGaAs/InGaAs HEMT quad, an active LO balun, and two passive baluns for RF and IF. At 16 dBm LO power, this mixer achieves the conversion losses of 7.5-9 dB for 4-13 GHz RF and 7.5-11 dB for 3-18 GHz RF. The SB mixer consists of a pair of AlGaAs/InGaAs HEMT's, an active LO balun, a passive IF balun and a passive RF power divider. At 16 dBm LO power, this mixer achieves the conversion losses of 8-10 dB for 4-15 GHz RF and 8-11 dB for 2-16 GHz RF. The simulated conversion losses of both mixers are very much in agreement with the measured results. Also, the DB mixer achieves a third-order input intercept (IP₃) of +19.5 to +27.5 dBm for a 7-18 GHz RF and 1 GHz IF at a LO drive of 16 dBm while the SB mixer achieves an input IP ₃ of +20 to +28.5 dBm for 2 to 16 GHz RF and 1 GHz IF at a 16 dBm LO power. The bandwidth of the RF and LO frequencies are approximately 6:1 for the DB mixer and 8:1 for the SB mixer. The DB mixer of this work is believed to be the first reported DB resistive HEMT MMIC mixer covering such a broad bandwidth     

An Ultra-Broadband Doubly Balanced Monolithic Ring Mixer for Ku- to Ka-band Applications

A novel 12-40 GHz ultra-broadband doubly balanced monolithic ring mixer with a small chip size covering the Ku- to Ka-band applications implemented by a 0.15-mum pseudo- morphic high electron-mobility transistor process is presented. The proposed mixer consists of two spiral transformer baluns and a band-reject filter. The use of the spiral baluns leads to the achievement of a chip size less than 0.8 times 0.8 mm². The radio frequency (RF) spiral balun with a band-reject filter served by an L-C resonator is used to improve the bandwidth of the mixer and to provide an output port for the intermediate frequency (IF) extraction as well. The mixer exhibits a 6-12 dB conversion loss, high isolation over 12-40 GHz RF/local oscillation bandwidth, a DC-8 GHz IF bandwidth, and a 1-dB compression power of 14 dBm for both down- and up-converter applications.     

Monolithic InGaP-GaAs HBT receiver front-end with 6 mW DC power consumption for 5 GHz band WLAN applications

A very low power consumption (6 mW) 5 GHz band receiver front-end using InGaP-GaAs HBT technology is reported. The receiver front-end is composed of a cascode low noise amplifier followed by a double-balanced mixer with the RF transconductor stage placed above the Gilbert quad for direct-coupled connection. The RF band of this receiver front-end is set to be 5.2 GHz, being downconverted to 1 GHz IF frequency. Input-return-loss (S/sub 11/) in RF port smaller than -12 dB and excellent power-conversion-gain of 35.4 dB are achieved. Input 1 dB compression point (P/sub 1dB/) and input third-order intercept point (IIP3) of -24 and -3 dBm, respectively, are also achieved.     

A 3.1-4.8 GHz CMOS receiver for MB-OFDM UWB

An integrated fully differential ultra-wideband CMOS receiver for 3.1-4.8 GHz MB-OFDM systems is presented. A gain controllable low noise amplifier and a merged quadrature mixer are integrated as the RF front-end. Five order Gm-C type low pass filters and VGAs are also integrated for both I and Q IF paths in the receiver. The ESD protected chip is fabricated in a Jazz 0.18 μm RF CMOS process and achieves a maximum total voltage gain of 65 dB, an AGC range of 45 dB with about 6 dB/step, an averaged total noise figure of 6.4 to 8.8 dB over 3 bands and an in-band lIP3 of-5.1 dBm. The receiver occupies 2.3 mm2 and consumes 110 mA from a 1.8 V supply including test buffers and a digital module.     

A 9–31-GHz Subharmonic Passive Mixer in 90-nm CMOS Technology

A subharmonic down-conversion passive mixer is designed and fabricated in a 90-nm CMOS technology. It utilizes a single active device and operates in the LO source-pumped mode, i.e., the LO signal is applied to the source and the RF signal to the gate. When driven by an LO signal whose frequency is only half of the fundamental mixer, the mixer exhibits a conversion loss as low as 8–11 dB over a wide RF frequency range of 9–31GHz. This performance is superior to the mixer operating in the gate-pumped mode where the mixer shows a conversion loss of 12–15dB over an RF frequency range of 6.5–20 GHz. Moreover, this mixer can also operate with an LO signal whose frequency is only 1/3 of the fundamental one, and achieves a conversion loss of 12–15dB within an RF frequency range of 12–33 GHz. The IF signal is always extracted from the drain via a low-pass filter which supports an IF frequency range from DC to 2 GHz. These results, for the first time, demonstrate the feasibility of implementation of high-frequency wideband subharmonic passive mixers in a low-cost CMOS technology.     

A 1.9-GHz silicon receiver with monolithic image filtering

A 1.9-GHz fully monolithic silicon superheterodyne receiver front-end is presented; it consists of a low noise amplifier (LNA), a tunable image reject filter, and a Gilbert cell mixer integrated in one die. The receiver was designed to operate with a 1.9-GHz RF and a 2.2-GHz local oscillator (LO) for a 300-MHz IF. Two chip versions were fabricated on two different fabrication runs using a 0.5-μm bipolar technology with 25 GHz transit frequency (f_T). Measured performance for the receiver front-end version 1, packaged and without input matching, was: conversion gain 33.5 dB, noise figure 4.9 dB, input IP3 -28 dBm, image rejection 53 dB (tuned to reject a 2.5-GHz image frequency), and 15.9 mA current consumption at +3 V. The image rejection was tunable from 2.4-2.63 GHz by means of an on-chip varactor. Version 2 had increased mixer degeneration for improved linearity. Its measured performance for the packaged receiver with its input matched to 50 Ω was: conversion gain 24 dB, noise figure 4.8 dB, input IP3 -19 dBm, and 65 dB image rejection for a 2.5-GHz image with an image tuning range from 2.34-2.55 GHz     

A Fully Integrated 60GHz Four Channel CMOS Receiver with 7GHz Ultra-Wide Bandwidth for IEEE 802.11ad Standard

In this paper, a fully integrated CMOS receiver frontend for high-speed short range wireless applications centering at 60GHz millimeter wave （mmW） band is designed and implemented in 90nm CMOS technology. The 60GHz receiver is designed based on the super-heterodyne architecture consisting of a low noise amplifier （LNA） with inter-stage peaking technique, a single- balanced RF mixer, an IF amplifier, and a double-balanced I/Q down-conversion IF mixer. The proposed 60GHz receiver frontend derives from the sliding-IF structure and is designed with 7GHz ultra-wide bandwidth around 60GHz, supporting four 2.16GHz receiving channels from IEEE 802.1lad standard for next generation high speed Wi- Fi applications. Measured results show that the entire receiver achieves a peak gain of 12dB and an input 1-dB compression point of -14.SdBm, with a noise figure of lower than 7dB, while consumes a total DC current of only 60mA from a 1.2V voltage supply.     

42GHz 波段接收机前端的设计与研制*

伴随着无线通信技术日新月异的发展,人们对宽频带、高速率、大容量通信系统的需求也日益增大.毫米波由于自身具有波长短、传输容量大等优点,日益受到研究人员的广泛关注和青睐.本文针对42GHz频段点对点高速通信应用,设计研制了该频段的毫米波接收机前端.该前端由三级低噪声放大器(LNA)、一级混频器和一个基片集成波导(siw)镜像抑制滤波器构成.射频(RF)信号工作在40.8GHz～ 42.8GHz频段内,中频(IF)固定在3.5GHz.测试结果显示,在工作频段内其变频增益大于15dB,射频输入功率ldB增益压缩点不低于-30dBm,接收机前端的噪声系数(NF)小于6dB.     

太赫兹宽带分谐波混频器设计

太赫兹分谐波混频器的变频损耗、噪声系数等指标与基波混频器相近,且本振频率为射频频率的一半,大大 降低了本振源的设计难度和制作成本,是高性能太赫兹接收前端的关键部件。本文介绍了一种覆盖全波导带宽的太赫 兹宽带分谐波混频器的设计,对电路中射频波导至悬置带线过渡结构和本振中频双工器进行仿真和优化设计。并以 0.14~0.22THz 分谐波混频器为例进行设计和制作,测试结果表明0.14 ~0.22THz 分谐波混频器在全波导频段内最大变频 损耗低于15dB,中频3dB 带宽大于20GHz。     

宽带低噪声混频器的设计

文章利用安捷伦公司的ADS仿真软件,设计了一款应用于GNSS接收机射频前端的Gilbert混频器芯片,它的工作电压都为3.3V,中频输出口外接负载为800Ω,具有面积小、噪声系数低的特点。通过优化设计,在频率从1~1.6GHz的范围内,获得了超过15dB的转换增益,以及4dB的噪声系数,输入1dB增益压缩点(P-1dB)为-17dBm,功耗为29mW。     

Highly integrated 60 GHz transmitter and receiver MMICs in a GaAs pHEMT technology

Highly integrated transmitter and receiver MMICs have been designed in a commercial 0.15 /spl mu/m, 88 GHz f/sub T//183 GHz f/sub MAX/ GaAs pHEMT MMIC process and characterized on both chip and system level. These chips show the highest level of integration yet presented in the 60 GHz band and are true multipurpose front-end designs. The system operates with an LO signal in the range 7-8 GHz. This LO signal is multiplied in an integrated multiply-by-eight (X8) LO chain, resulting in an IF center frequency of 2.5 GHz. Although the chips are inherently multipurpose designs, they are especially suitable for high-speed wireless data transmission due to their very broadband IF characteristics. The single-chip transmitter MMIC consists of a balanced resistive mixer with an integrated ultra-wideband IF balun, a three-stage power amplifier, and the X8 LO chain. The X8 is a multifunction design by itself consisting of a quadrupler, a feedback amplifier, a doubler, and a buffer amplifier. The transmitter chip delivers 3.7/spl plusmn/1.5 dBm over the RF frequency range of 54-61 GHz with a peak output power of 5.2 dBm at 57 GHz. The single-chip receiver MMIC contains a three-stage low-noise amplifier, an image reject mixer with an integrated ultra-wideband IF hybrid and the same X8 as used in the transmitter chip. The receiver chip has 7.1/spl plusmn/1.5 dB gain between 55 and 63 GHz, more than 20 dB of image rejection ratio between 59.5 and 64.5 GHz, 10.5 dB of noise figure, and -11 dBm of input-referred third-order intercept point (IIP3).     

3-D Integration of 10-GHz Filter and CMOS Receiver Front-End

A 10-GHz filter/receiver module is implemented in a novel 3-D integration technique suitable for RF and microwave circuits. The receiver designed and fabricated in a commercial 0.18-mum CMOS process is integrated with embedded passive components fabricated on a high-resistivity Si substrate using a recently developed self-aligned wafer-level integration technology. Integration with the filter is achieved through bonding a high-Q evanescent-mode cavity filter onto the silicon wafer using screen printable conductive epoxy. With adjustment of the input matching of the receiver integrated circuit by the embedded passives fabricated on the Si substrate, the return loss, conversion gain, and noise figure of the front-end receiver are improved. At RF frequency of 10.3 GHz and with an IF frequency of 50 MHz, the integrated front-end system achieves a conversion gain of 19 dB, and an overall noise figure of 10 dB. A fully integrated filter/receiver on an Si substrate that operates at microwave frequencies is demonstrated.     

A 0.7-7 GHz wideband reconfigurable receiver RF front-end in CMOS

In this paper,a 0.7-7 GHz wideband RF receiver front-end SoC is designed using the CMOS process.The front-end is composed of two main blocks:a single-ended wideband low noise amplifier (LNA) and an inphase/quadrature (I/Q) voltage-driven passive mixer with IF amplifiers.Based on a self-biased resistive negative feedback topology,the LNA adopts shunt-peaking inductors and a gate inductor to boost the bandwidth.The passive down-conversion mixer includes two parts:passive switches and IF amplifiers.The measurement results show that the front-end works well at different LO frequencies,and this chip is reconfigurable among 0.7 to 7 GHz by tuning the LO frequency.The measured results under 2.5-GHz LO frequency show that the front-end SoC achieves a maximum conversion gain of 26 dB,a minimum noise figure (NF) of 3.2 dB,with an IF bandwidth of greater than 500 MHz.The chip area is 1.67 × 1.08 mm2.