基于交叉开关结构的片上光互连网络研究

最近一些研究小组提出光片上网络以解决现有电片上网络无法满足未来片上系统(SoC)高带宽、高能效要求的问题。光交叉开关作为光互连中必不可少的一部分,既可以用于光路由器的设计中,又可以用来构建一个全互连的网络。文章综述了交叉开关的发展,并对现阶段提出的光交叉开关结构在能耗与通信过程方面进行了分析、对比。最后结合实例研究了光交叉开关在光片上网络中的应用,结果表明光交叉开关在光互连中具有很好的应用前景。     

片内光通信技术综述

在纳米工艺水平下,传统的铜线互连已经很难满足集成电路芯片在延迟、带宽、功耗等方面的要求,片内通信问题已经成为集成电路设计的瓶径.文中根据片内光器件集成技术的最新进展,介绍了采用片内光互连代替电互连的最新技术及其性能方面的优势.文中重点总结了片内光互连的三种典型应用.首先,介绍了片内光时钟分布网络;其次,从应用的角度分析了光电总线结构相对于单纯电总线在性能上的提升;最后,介绍了一种新的片上光网络,它集成了片内电的包交换控制网络和宽带电路交换光网络.仿真和实验结果表明,光互连能够为高集成度纳米级芯片提供高带宽、低延迟,小功耗的片内通信服务.     

片上网络:新一代的片上系统结构

片上系统是使用共享或专用总线作为芯片的通信资源.由于这些总线具有一定的限制,因此扩展性较差,不能满足发展需求.在这种情况下,目前的片内互连结构将成为多核芯片的发展瓶颈.文章介绍了一种新型的片上体系结构(片上网络)来解决未来片上系统中总线所带来的不足.片上网络作为一种新的片上体系结构,可以解决片上系统设计中所带来的各种挑...     

光互连技术及其在计算机中的应用

自１９８４年国际著名的光学专家Ｊ．Ｗ．Ｇｏｏｄｍａｎ提出在ＶＬＳＩ系统中采用光互连技术以来,光互连技术已经取得很大进展,并开始代替电互连对计算机性能的提高产生影响。光互连技术已被广泛地接受为改善通信瓶颈的一种有效方法,并正在大步地走向实用。随着微光学技术、光学材料、光电子器件技术和多芯片集成技术的发展,高密度两维光互连已成为现实,这为电子计算机发展新结构开辟了新的道路。 光互连的特性 光波的属性 互连是指短距离上的信号传递,在计算机中目前的互连方式主要是印制电路板上的微带和导线。与电互连的电流信号…     

一种基于微环的新型4×4非阻塞光路由开关

光互连技术因诸多特性优于电互连而成为片上多核互连最具前景的解决方案。为了提高片上光互连网络架构的性能,采取光器件模块搭建的方法,提出了一种基于微环的新型4×4光路由开关,仅用7个微环构建的拓扑结构便实现了4个双向端口的非阻塞交换,降低了功耗和面积;波导交叉的数量减少到6个,优化了插入损耗。结果表明,该结构相对于经典结构光器件的功耗节省了约8%,光互连层的插入损耗降低了约7%。     

超高速光互连系统级封装技术前沿研究

光互连系统级封装技术是用光互连在封装尺度上代替铜互连,以突破目前芯片间通信低速度瓶颈。超高速光互连系统级封装的目标是开发出可集成光子收发器,并嵌入到现代尖端的系统级封装中(SiP)中,以提高并行计算系统的数据传输效率或速度。文章介绍了超高速光互连系统级封装关键技术及前沿研究情况,通过分析IMEC、Intel、BAE系统公司等研究机构的开发现状和技术发展路线,论述了光互连SiP关键技术的发展趋势。     

集成电路芯片上光互连研究的新进展

讨论了集成电路向高集成度、高工作频率和高传输速率继续发展时 ,常规金属互连出现的困难以及集成电路芯片上光互连具有的潜在优势 .介绍了组成芯片上光互连的光发射器件、光接收器件和光传输器件等三种基本器件及其与硅集成电路集成的研究新进展 .最后展望了集成电路芯片上光互连的应用前景 .     

集成电路芯片上光互连研究的新进展

讨论了集成电路向高集成度、高工作频率和高传输速率继续发展时,常规金属互连出现的困难以及集成电路芯片上光互连具有的潜在优势．介绍了组成芯片上光互连的光发射器件、光接收器件和光传输器件等三种基本器件及其与硅集成电路集成的研究新进展．最后展望了集成电路芯片上光互连的应用前景．     

光互连研究进展

光互连在高度并行、高速、大容量的数字系统和智能计算等领域显示了卓越的潜能。文章首先比较了在超大规模集成系统（ＶＬＳＩ）中光互连和电互连的优劣,总结了各种类的光互连及近年取得的新进展,并分析了光互连遇到的困难和未来前景。     

有机聚合物光波导制作工艺综述

有机聚合物光波导光互连已成为实现短距离计算通信设计目标的最佳解决方法。短距离光互连是未来互连方向,综合性能优良的聚合物多模光波导是光互连中的重要组成部分。有机聚合物光波导的制作工艺对光波导的性能具有重要影响,故此对有机聚合物光波导的制作工艺进行了综述,并提出了一些未来的研发方向。     

Optimal global interconnects for GSI

Performance of a high-speed chip is largely affected by both latency and bandwidth of global interconnects, which connect different macrocells. Therefore, one of the important goals is to design high-bandwidth and fast buses that connect a processor and its on-chip cache memory or link different processors within a multiprocessor chip. In this paper, the width of global interconnects is optimized to achieve a large "data-flux density" and a small latency simultaneously. Data-flux density is the product of interconnect bandwidth and reciprocal wire pitch, which represents the number of bits per second that can be transferred across a unit-length bisectional line. The optimal wire width, which maximizes the product of data-flux density and reciprocal latency, is independent of interconnect length and can be used for all global interconnects. It is rigorously proved that the optimal wire width is the width that results in a delay that is 33% larger than the time-of-flight (ToF). Using the optimal wire width decreases latency, energy dissipation, and repeater area considerably, compared to a sub-optimal wire width (e.g., 42% smaller latency, 30% smaller energy-per-bit, and 84% smaller repeater area compared with the W/sub opt//2 case) at the cost of a small decrease in data-flux density (e.g., 14% smaller compared with W/sub opt//2 case). A super-optimal wire width, however, causes a slight decrease in latency (e.g., 14% for 2W/sub opt/) at the cost of a large decrease in data-flux density (e.g., 35% for 2W/sub opt/).     

Wafer-level package interconnect options

As integrated circuit technology enters the nanometer era, global interconnects are becoming a bottleneck for overall chip performance. In this paper, we show that wafer-level package interconnects are an effective alternative to conventional on-chip global wires. These interconnects behave as LC transmission lines and can be exploited for their near speed of light transmission and low attenuation characteristics. We compare performance measures such as bandwidth, bandwidth density, latency, and power consumption of the package-level transmission lines with conventional on-chip global interconnects for different International Technology Roadmap for Semiconductors (ITRS) technology nodes. Based on these results, we show that package-level interconnects are well suited for power demanding low-latency applications. We also analyze different interconnect options such as memory buses, long inter tile interconnects, clock, and power distribution.     

Trend and Challenge on System-on-a-Chip Designs

The success of system-on-a-chip (SoC) hinges upon a well-concerted integrated approach from multiple disciplines, such as device, design, and application. From the device perspective, rapidly improving VLSI technology allows the integration of billions of transistors on a single chip, thus permitting a wide range of functions to be combined on one chip. From the application perspective, numerous killer applications have been identified, which can make full use of the aforementioned functionalities provided by a single chip. From the design perspective, however, with greater device integration, system designs become more complex and are increasingly challenging to design. Moving forward, novel approaches will be needed to meet these challenges. This paper explores several new design strategies, which represent the current design trends to deal with the emerging issues. For example, recognizing the stringent requirements on power consumption, memory bandwidth/latency, and transistor variability, novel power/thermal management, multi-processor SoC, reconfigurable logic, and design for verification and testing have now been incorporated into modern system design. In addition, we look into some plausible solutions. For example, further innovations on scalable, reusable, and reliable system architectures, IP deployment and integration, on-chip interconnects, and memory hierarchies are all anticipated in the near future.     

A Chip-Stacked Memory for On-Chip SRAM-Rich SoCs and Processors

A dynamic-reconfigurable memory chip is fabricated, by which on-chip memories of an SoC chip can be moved to the memory chip to increase the efficiency of memory usage, and stacked on a logic chip by using three dimensional packaging technology. In the memory chip, many RAM-macros are arrayed and they are connected through two dimensional mesh network interconnects. By using memory-specified network interconnects, area overhead of network interconnects for the memory chip is reduced by 63% and the latency overhead by 43%. Signal lines between the two chips are directly connected by 10-?m-pitch inter-chip electrodes, resulting in fast and low-energy inter-chip transmission.     

Predictions of CMOS compatible on-chip optical interconnect

Interconnect has become a primary bottleneck in the integrated circuit design process. As CMOS technology is scaled, the design requirements of delay, power, bandwidth, and noise due to the on-chip interconnects have become more stringent. New design challenges are continuously emerging, such as delay uncertainty induced by process and environmental variations. It has become increasingly difficult for conventional copper interconnect to satisfy these design requirements. On-chip optical interconnect has been considered as a potential substitute for electrical interconnect. In this paper, predictions of the performance of CMOS compatible optical devices are made based on current state-of-the-art optical technologies. Electrical and optical interconnects are compared for various design criteria based on these predictions. The critical dimensions beyond which optical interconnect becomes advantageous over electrical interconnect are shown to be approximately one-tenth of the chip edge length at the 22 nm technology node.     

Performance Comparisons Between Carbon Nanotubes, Optical, and Cu for Future High-Performance On-Chip Interconnect Applications

Optical interconnects and carbon nanotubes (CNTs) present promising options for replacing the existing Cu-based global/semiglobal (optics and CNT) and local (CNT) wires. We quantify the performance of these novel interconnects and compare it with Cu/low-kappa wires for future high-performance integrated circuits. We find that for a local wire, a CNT bundle exhibits a smaller latency than Cu for a given geometry. In addition, by leveraging the superior electromigration properties of CNT and optimizing its geometry, the latency advantage can be further amplified. For semiglobal and global wires, we compare both optical and CNT options with Cu in terms of latency, energy efficiency/power dissipation, and bandwidth density. The above trends are studied with technology node. In addition, for a future technology node, we compare the relationship between bandwidth density, power density, and latency, thus alluding to the latency and power penalty to achieve a given bandwidth density. Optical wires have the lowest latency and the highest possible bandwidth density using wavelength division multiplexing, whereas a CNT bundle has a lower latency than Cu. The power density comparison is highly switching activity (SA) dependent, with high SA favoring optics. At low SA, optics is only power efficient compared to CNT for a bandwidth density beyond a critical value. Finally, we also quantify the impact of improvement in optical and CNT technology on the above comparisons. A small monolithically integrated detector and modulator capacitance for optical interconnects (~10 fF) yields a superior power density and latency even at relatively lower SA (~20%) but at high bandwidth density. At lower bandwidth density and SA lower than 20%, an improvement in mean free path and packing density of CNT can render it most energy efficient.     

Global interconnect width and spacing optimization for latency, bandwidth and power dissipation

This paper addresses a novel methodology optimizing global interconnect width and spacing for International Technology Roadmap for Semiconductors technology nodes. Global interconnects with and without buffer insertion are considered. The effects of the width and spacing of global interconnects on performance, such as delay, bandwidth, total repeater area and energy dissipation, are analyzed. The product of delay and bandwidth is used as the figure of merit for simultaneous short latency and large bandwidth and the proposed methodology can optimize global interconnects for the maximal figure of merit. It is demonstrated that buffers should not be inserted in global interconnects if interconnect length is shorter than a critical length, which is a constant for a given technology. For global interconnects with buffer insertion, the optimal width and spacing have analytical expressions and are constants for a given technology. For global interconnects without buffer insertion, the optimal width and spacing are dependent on both the technology parameters and interconnect length and can be computed numerically.     

System-level modeling and performance evaluation of multistage optical network on chips (MONoCs)

With the number of CPU cores on a processor chip increasing rapidly, conventional electronic interconnects for core-to-core communication have run into a bottleneck. Recently, rapid development has been achieved for photonic technologies, which makes optical network on chip become an emerging solution to breakthrough electronic interconnect limitations. Multistage optical network on chips (MONoCs), by adopting multiple stages in the architecture, have great potentials to achieve the advantages of energy efficiency, high performance and scalability. To benefit from these advantages, we design a novel system-level model for MONoCs, which allows us to evaluate the performance by modeling and analyzing the latency, loss and crosstalk. The model is validated by simulation, which demonstrates that we can identify and predict some potential problems, such as latency jitter and asymmetry insertion loss distribution. Results show that our proposed model can provide insightful guidance for designing multistage optical network on chip.     

Design and Performance Modeling for Single-Walled Carbon Nanotubes as Local, Semiglobal, and Global Interconnects in Gigascale Integrated Systems

Based on physical models, distributed circuit models are presented for single-walled carbon nanotubes (SWCNs) and SWCN bundles that are valid for all voltages and lengths. These models can be used for circuit simulations and compact modeling. It is demonstrated that by customizing SWCN interconnects at the local, semiglobal, and global levels, several major challenges facing gigascale integrated systems can potentially be addressed. For local interconnects, monolayer or multilayer SWCN interconnects can offer up to 50% reduction in capacitance and power dissipation with up to 20% improvement in latency if they are short enough (<20 mum). For semiglobal interconnects, either latency or power dissipation can be substantially improved if bundles of SWCNs are used. The improvements increase as the cross-sectional dimensions scale down. For global interconnects, bandwidth density can be improved by 40% if there is at least one metallic SWCN per 3-nm² cross-sectional area     

Compact Performance Models and Comparisons for Gigascale On-Chip Global Interconnect Technologies

The on-chip global interconnect with conventional Cu/low-k and delay-optimized repeater scheme faces great challenges in the nanometer regime owing to its severe performance degradation. This paper describes the analytical models and performance comparisons of novel interconnect technologies and circuit architectures to cope with the interconnect performance bottlenecks. Carbon nanotubes (CNTs) and optics-based interconnects exhibit promising physical properties for replacing the current Cu/low-k-based global interconnects. We quantify the performance of these novel interconnects and compare them with Cu/low-k wires for future high-performance integrated circuits. The foregoing trends are studied with technology node and bandwidth density in terms of latency and power dissipation. Optical wires have the lowest latency and power consumption, whereas a CNT bundle has a lower latency than Cu. The new circuit scheme, i.e., “capacitively driven low-swing interconnect (CDLSI),” has the potential to effect a significant energy saving and latency reduction. We present an accurate analytical optimization model for the CDLSI wire scheme. In addition, we quantify and compare the delay and energy expenditure for not only the different interconnect circuit schemes but also the various future technologies, such as Cu, CNT, and optics. We find that the CDLSI circuit scheme outperforms the conventional interconnects in latency and energy per bit for a lower bandwidth requirement, whereas these advantages degrade for higher bandwidth requirements. Finally, we explore the impact of the CNT bundle and the CDLSI on a via blockage factor. The CNT shows a significant reduction in via blockage, whereas the CDLSI does not help to alleviate it, although the CDLSI results in a reduced number of repeaters due to the differential signaling scheme.