用于相控阵雷达的高线性度低噪声放大器

基于IBM 0.18 μm SiGe BiCMOS工艺,提出了一种用于Ku波段相控阵雷达的高线性度低噪声放大器。该放大器采用2级级联结构,第1级优化可获得最小的噪声性能,第2级优化可提高电路的增益和线性输出功率。为了提高线性度,第2级采用了具有线性补偿功能的线性化偏置电路。仿真结果表明,在中心频率为16.5 GHz,带宽为2 GHz的频带范围内,噪声系数小于3.9 dB,其最小值为3.22 dB,功率增益大于23.5 dB,输出1-dB压缩点在中心频率处大于6.5 dBm。在3.3 V电源电压下,静态功耗为66 mW,芯片面积为(1 245×580) μm²。     

一种2.5 Gb/s LVDS接收器设计

基于SMIC 0.18 μm 1P6M 标准CMOS工艺,设计了一种2.5 Gb/s LVDS接收器电路。仿真结果表明,所设计的LVDS电路参数符合LVDS标准,LVDS接收器的输出信号上升沿抖动约为0.76 ps,有效版图面积约为(83×44) μm²,能应用于高速数据接口。     

适用于连续数据速率CDR的相位插值器研制

通过对相位插值器电路进行建模分析,得到了相位插值器的线性度与输入信号之间相位差、输入信号上升时间和输出节点时间常数的关系.根据分析得到的结论,提出了一种新型的应用于连续数据速率时钟数据恢复电路的相位插值器,通过在相位插值器之前插入延时可控的缓冲器,使其输入信号的上升时间可以跟踪数据速率的改变,在保证线性度的同时,降低电路的噪声敏感度和功耗.芯片采用Charlerd 0.13 μm低功耗1.5/3.3 V工艺流片验证,面积为0.02 mm2,数据速率3.125 Gb/s时,功耗为8.5 mW.     

Imaging one-dimensional and two-dimensional planar photodiode detectors fabricated by ion milling molecular beam epitaxy CdHgTe

Imaging one-dimensional (1-D) and two-dimensional (2-D) arrays of mid-wavelength infrared (MWIR) and long-wavelength infrared (LWIR) planar photodiodes were fabricated by ion milling of vacancy-doped molecular beam epitaxy Cd_xHg_1−xTe layers. Sixty-four-element 1-D arrays of 26×26 μm² or 26×56 μm² diodes were processed. Zero-bias resistance-area values (R₀A) at 77 K of 4×10⁶ Θcm² at cutoff wavelength λ_CO=4.5 μm were measured, as well as high quantum efficiencies. To avoid creating a leakage current during ball bonding to the 1-D array diodes, a ZnS layer was deposited on top of the CdTe passivation layer, as well as extra electroplated Au on the bonding pads. The best measured noise equivalent temperature difference (NETD) on a LWIR array was 8 mK, with a median of 14 mK for the 42 operable diodes. The best measured NETD on a MWIR array was 18 mK. Two-D arrays showed reasonably good uniformity of R₀A and zero-bias current (I₀) values. The first 64×64 element 2-D array of 16×16 μm² MWIR diodes has been hybridized to read-out electronics and gave median NETD of 60 mK.     

Electrical-efficiency analysis of GaN-based light-emitting diodes with interdigitated-mesa geometry

We propose a novel method to analyze the current-voltage (I-V) characteristics of GaN-based light-emitting diodes (LEDs) with different p-type electrodemesa geometries. The electrical efficiency is analyzed by calculating the electric field under the quasi-coplanar electrodes of GaN-based LEDs. The experimental results for GaN-based LEDs of chip sizes of 350×350 μm² and 1,000 × 1,000 μm² with interdigitated fingers are compared. A good agreement is obtained between the experimental and theoretical electrical efficiency of the GaN LEDs with a chip size of 1,000×1,000 μm². The current-crowding effect is analyzed by measuring the electroluminescence spectra of the devices. The result indicates that the current-crowding effect is largely reduced by increasing the number of interdigitated fingers. The electrical efficiency of a LED with a chip size of 1,000×1,000 μm² can be also enhanced by increasing the number of interdigitated fingers, showing the advantages of GaN LED with interdigitated-mesa geometries.     

一种5 Gb/s双信道并行时钟数据恢复电路

基于0.18 μm CMOS工艺,设计了一种双信道并行时钟数据恢复(CDR)电路,它由1个锁相环(PLL)型CDR和1个相位选择/相位插值(PS/PI)型CDR结合实现。与传统的并行CDR相比,该CDR电路不需要本地参考时钟。PLL型CDR中环形压控振荡器的延迟单元采用电感峰化技术,拓展了带宽,实现了较高的振荡频率;电荷泵采用自举基准和运放,改善了充放电电流匹配。PS/PI型CDR中Bang-Bang型鉴相器结构简单,具有较好的鉴相功能;PS/PI电路比传统结构少2个相位选择器。仿真结果表明,当输入并行数据速率为5 Gb/s时,恢复出的2组时钟与数据的峰峰抖动值分别为6.1 ps,8.1 ps和8.7 ps,11.2 ps。电路核心模块的功耗为172.4 mW,整体电路版图面积为(1.7×1.585) mm²。     

采用相邻采样求和的突发模式相位插值型CDR

提出了一种具有良好抑制输入数据抖动性能的突发模式相位插值型时钟数据恢复电路。在传统相位插值型电路结构的基础上,在采样保持电路与相位插值电路之间加入一级求和电路,理论分析和仿真结果表明,恢复时钟相位变化受输入数据抖动的影响明显减小。电路基于1.1 V SMIC 40 nm 1P8M CMOS工艺搭建,其数据率为6.25 Gb/s,消耗功耗为6.7 mW,版图面积为0.35 mm²。     

一种基于自偏置技术的低功耗锁相环设计

采用TSMC 0.13 μm CMOS工艺,设计并实现了一种低功耗、具有固定的环路带宽与工作频率之比,以及良好相位噪声性能的自偏置锁相环(PLL)芯片电路。仿真结果表明,该PLL电路工作频率范围为200~800 MHz,在480 MHz输出频率的相位噪声为-108 dBc@1 MHz,1.2 V电源供电下消耗功耗2 mW。芯片核心电路面积仅为0.15 mm²,非常适合应用于系统集成。     

一种2.2~4 GHz高增益低噪声放大器

采用0.25 μm GaAs赝配高电子迁移率晶体管(pHEMT)工艺,设计并实现了一种应用于5G通信2.2~4 GHz频段的高增益共源共栅低噪声放大器(LNA)。通过将并联RC负反馈与共栅接地电容结合,不使用源极电感,实现了宽带高增益的LNA设计。测试结果表明,2.2~4 GHz频段增益大于24 dB,输出3阶互调(OIP3)为28 dBm,噪声系数(NF)小于0.78 dB,功耗为190 mW,芯片面积为(810×710) μm²。综合指标(FOM)为14.4 dB,与同类LNA相比具有一定的优势。     

基于15位像素级模数转换器的640×512规格中波红外成像用48 mW数字读出电路

提出了一种用于中波红外成像的基于15位像素级单斜率模数转换器的低功耗数字读出电路。像素级模数转换器采用一种新型功耗自适应的脉冲输出型比较器,只有当斜坡电压信号接近积分电压时,比较器才产生功耗。此外,比较器输出脉冲信号,降低了15位量化结果存储器上消耗的动态功耗。该存储器采用三管动态结构,仅占约54 μm²面积,以满足15 μm像素中心距的面积约束。量化结果以电流模式读出到列级,避免相邻列总线间的电压串扰。基于0.18 μm CMOS工艺,采用该结构,设计并制造了640×512 规格的数字读出电路。测试结果表明,在120 Hz的帧频下,功耗仅为48 mW,总积分电容为740 fF,电荷处理能力为8.8 Me^-。在满阱状态,等效到积分电容的噪声电压为116 μV,峰值信噪比为84 dB。