直流对数放大器

直流对数放大器是放大倍数随输入信号的大小按对数规律变化的直流放大器。这种放大器输入动态范围大,输入和输出成对数关系。一、直流对数放大器的基本原理直流对数放大器由直流放大器和提供对数特性的反馈元件两部分组成。提供对数特性的反馈元件通常是晶体二极管或是接成二极管形式的晶体三极管。图1是直流对数放大器的原理图。从图1中可以看到,由于直流放大器A的反馈元件的电压与电流的对数成比例,因此,使整个放大器的输出电压与输入电压的对数成比例。其数字表达式为 (1)式中L_ε是反馈元件BG的发射极-基极结反向饱和电流;α是一常数。证明如下:     

加速自校正直流漂移的可编程增益放大器

设计了一种应用于移动数字多媒体广播系统终端的可编程增益放大器.该可编程增益放大器采用源极反馈电阻可变的差分放大器结构,且带有直流漂移校正电路.分析了校正直流漂移时间的决定因素,通过采用双带宽切换的方法加速校正过程.分析了引发输出直流漂移发生变化的因素,设计了增益控制信号触发的双带宽控制信号发生电路.可编程增益放大器采用TSMC 0.25μm CMOS工艺.仿真结果表明,放大器的动态范围为30~84db,2db步进,对输入直流漂移的校正效果为-21.45db,加速后的直流漂移校正时间约15μs.     

重视音质设计的MUSES运算放大器（上）

大家知道,当初运算放大器（OP）是作为模拟电子计算机的运算电路使用的,其用途仅限于直流放大器。后来出现了集成（IC）化的单片运算放大器,具有很高的直流增益、很低的漂移,体积小,成本又低,不仅能用于直流放大,还能用于交流放大。     

电子百科

零漂移放大器 零漂移放大器是指失调电压漂移接近于0的放大器。它连续自动校正任何直流误差,实现超低水平的失调电压、时间漂移和温度漂移。零漂移放大器的常见特性包括：超低失调电压和漂移、高开环增益、高电源抑制、高共模抑制以及零1/f噪声。     

直流式温控电路零漂的补偿

推导出运算放大器零点漂移的计算公式，介绍了恒温晶体振荡器的直流式恒温电路的恒温原理及零点漂移的补偿方法。     

小漂移的晶体管直流放大器

这篇论文叙述在设计小漂移直流放大器中重要的晶体管直流参数的变化.叙述改进性能所必须的习惯上的“长引线对”及其变形,并估计它的结果.然后叙述一种新的,平衡的,“镜像”放大器并讨论其性能和作用.最后,指出设计直接偶合放大器的发展趋势.     

直流式温控电路零漂的补偿

推导出运算放大器零点漂移的计算公式，介绍了恒温晶体振荡器的直流式恒温电路的恒温原理及零点漂移的补偿方法。     

SB523宽带对数放大器

介绍了一种采用硅双极工艺制造的用于连续检波式对数放大器的单元电路。该电路由两级限幅放大器直流耦合、两级具有对数特性的负极性检波器并联组成，小信号电压增益为２４ｄＢ、动态范围为２４ｄＢ。四级该电路级联成的对数放大器，其动态范围可达８０ｄＢ。着重介绍了该单元电路的原理、制造工艺、版图设计和应用     

光接收机用0.5mV高灵敏度带有接收信号强度指示的200MbpsCMOS限幅放大器

采用CSMC 0.6μm 2P2M CMOS工艺设计并实现了0.5mV高灵敏度,72dB超宽动态范围的200Mbps CMOS限幅放大器.该电路详细分析和设计了一种新型的有源直流漂移消除环路获得这一性能.利用信号通路中的限幅放大器,实现了基于分段线性近似的接收信号强度指示电路.信号检测的动态范围高达60dB,对数精度小于2dB.整个电路在5V单电源下工作,功耗为60mW.芯片有效面积为1.05mm2.     

光接收机用0.5mV高灵敏度带有接收信号强度指示的200Mbps CMOS限幅放大器

采用CSMC 0.6μm 2P2M CMOS工艺设计并实现了0.5mV高灵敏度,72dB超宽动态范围的200Mbps CMOS限幅放大器.该电路详细分析和设计了一种新型的有源直流漂移消除环路获得这一性能.利用信号通路中的限幅放大器,实现了基于分段线性近似的接收信号强度指示电路.信号检测的动态范围高达60dB,对数精度小于2dB.整个电路在5V单电源下工作,功耗为60mW.芯片有效面积为1.05mm2.     

CMOS linear-in-dB VGA with DC offset cancellation for direct-conversion receivers

A low-power high-linearity linear-in-dB variable gain amplifier(VGA) with novel DC offset calibration loop for direct-conversion receiver(DCR) is proposed.The proposed VGA uses the differential-ramp based technique,a digitally programmable gain amplifier(PGA) can be converted to an analog controlled dB-linear VGA. An operational amplifier(OPAMP) utilizing an improved Miller compensation approach is adopted in this VGA design.The proposed VGA shows a 57 dB linear range.The DC offset cancellation(DCOC) loop is based on a continuous-time feedback that includes the Miller effect and a linear range operation MOS transistor to realize high-value capacitors and resistors to solve the DC offset problem,respectively.The proposed approach requires no external components and demonstrates excellent DCOC capability in measurement.Fabricated using SMIC 0.13μm CMOS technology,this VGA dissipates 4.5 mW from a 1.2 V supply voltage while occupying 0.58 mm~2 of chip area including bondpads.In addition,the DCOC circuit shows 500 Hz high pass cutoff frequency(HPCF) and the measured residual DC offset at the output of VGA is less than 2 mV.     

Analysis of the Effect of Radio Frequency Interference on the DC Performance of CMOS Operational Amplifiers

Fourier-series approximations are obtained for the input-output characteristic of the CMOS asymmetrical differential amplifier. Using these approximations, the DC current offset of a CMOS differential amplifier subjected to RF interference can be studied and analytical expressions are obtained. These expressions can help in optimizing the parameters of the CMOS differential amplifier to minimize the offset current resulting from the RF interference.     

Operational amplifier input stage robust to EMI

Radio frequency interference superimposed on the input nominal signals of an operational amplifier excites distortion phenomena in active nonlinear devices. In actual differential input stages, interference generates even-order harmonics and in particular DC offset voltage. A new frequency selective input differential stage is presented, which minimises the generation of DC offset voltage due to distortion phenomena     

Improved common-mode feedback circuit suitable for operational transconductance amplifiers with tuning

A simple modification is proposed for a popular common-mode feedback circuit used in operational amplifiers, such that it can be used in an operational transconductance amplifier (OTA) without leading to significant DC offset caused by the unavoidable tuning of the OTA. Simulation results show that the improved circuit has nearly zero DC offset for the whole tuning range.<>     

Temperature compensated logarithmic peak detector

A temperature compensated logarithmic amplifier for signal strength indicator or automatic gain control applications is presented. The logarithmic function is realized with a current-feedback operational amplifier with a nonlinear diode feedback. The designed BiCMOS current-feedback operational amplifier utilizes a novel circuit topology which makes possible constant 1 MHz bandwidth amplification with closed loop voltage gains up to 60 dB. The offset current of the current-feedback amplifier is cancelled with an active OTA-C feedback loop. The logarithmically amplified signal is further processed by a peak detector and a temperature compensation circuit. The temperature compensation principle is based on a division of two v _BE:s and it is realized with a current controlled variable current mirror. The logarithmic amplifier is fabricated with a 1.2 micron BiCMOS-process with NPN's f_T of 7 GHz. The power consumption of the circuit is 25 mW with a 4.5 V supply voltage.     

Efficient reduction of electromagnetic interference effects in operational amplifiers

When subjected to electromagnetic interference, an operational amplifier will generate a DC offset. A thorough comparison between two approaches to reduce this offset is presented. Through mathematical deduction and simulations, it is shown that placing a lowpass filter at the input differential pair is superior to a double differential pair compensation topology     

Threshold difference compensated sense amplifier

A dynamic flip-flop sense amplifier compensating for threshold difference between a pair of transistors by way of offset storage technique is presented. The DC and AC analyses on input offset voltage and performance limitations are discussed. Experimental results have shown that input offset is less than 2 mV with a 5 V single power supply, over a wide temperature range and a wide common mode input voltage range.     

Noise Analysis and Optimization of Programmable Gain Amplifier with DC Offset Cancelation

The noise contribution of a DC offset cancelation (DCOC) circuit in a programmable gain amplifier (PGA) is studied for the first time in this paper. The analysis presented shows that the DCOC-induced noise may deteriorate the PGA’s noise performance significantly if we do not pay enough attention to it. For an analog DCOC (ADCOC), it is concluded that the PGA’s noise increases rapidly as the output DC offset decreases, thereby causing difficulties to achieve both low noise and low DC offset simultaneously. We propose an optimization technique that can effectively alleviate the noise issue by increasing the feedback amplifier’s gain and the resistor’s value simultaneously, while maintaining a reasonable DC gain. For a digital DCOC (DDCOC), the extra noise comes from the transistors of the current source (sink) bank. The transistors with a longer channel length are preferred for their lower thermal and flicker noise current. The proof-of-concept prototypes are designed in a 0.18-\(\upmu \)m CMOS process, and a 3-stage PGA with ADCOC is fabricated. The measurement results validate the analysis and simulation results well.     

A novel low-power transceiver topology for noncontact vital sign detection including the power management technique

In this paper, power management technique utilized in the direct down-conversion non-quadrature transceiver is presented for the low-power application of vital sign detection. The simultaneous switching noise (SSN) and overshoot and undershoot of the transient waveform distortion resulting from a pulse signal will give rise to interference with a vital sign signal. The pulse width, rise/fall time, and period of pulse bias are analyzed to mitigate the interference in this investigation. Significant issues about direct-current (DC) offset and noise confronted by the presented technique are addressed based on mathematical analysis. In radio-frequency (RF) transceiver architecture including power amplifier (PA), low-noise amplifier (LNA), and mixer, the current-reused (CRU) topology is utilized to achieve low DC power consumption. The post-layout simulation results exhibit that power consumption of the transceiver using the optimized pulse bias is reduced to 40% of the power consumption for transceiver applying the DC bias. In addition, DC offset and null detection point can be alleviated by tunable phase shifter.