Sn0.7Cu无铅焊点的电迁移失效模拟及优化分析

基于ANSYS有限元软件,综合考虑电子风力、温度梯度、应力梯度和原子密度梯度四种电迁移驱动机制,采用原子密度积分法(ADI)对倒装芯片球栅阵列封装(FCBGA)的Sn0.7Cu无铅焊点进行电迁移失效模拟。针对焊点直径、焊点高度、焊点下金属层(UBM)厚度三个关键参数进行电迁移失效的正交试验优化,探究焊点尺寸对电迁移失效的影响。研究表明:焊点直径和高度的增加会缩短焊点的电迁移失效寿命(TTF),而UBM层厚度对焊点失效寿命的影响相对较小;焊点局部拉应力对焊点的失效寿命影响较大,通常会加剧焊点的空洞失效。     

一种电迁移测试失效时间判定方法

采用铜大马士革工艺制备了用于电迁移测试的样品,对电迁移测试过程中存在的两类电阻-时间(R-t)特征曲线进行了研究.研究发现采用固定电阻变化率作为失效判定标准所得的失效时间分布曲线不能真实地反映样品的实际寿命,而采用第一次阻值跳变点对应的时间作为失效时间所得的分布曲线则更符合电迁移理论.针对两种失效判定方法所得到的不同结果进行了机理分析,结果表明,采用第一次阻值跳变点对应的时间作为失效时间分析电迁移失效更合理.     

应力诱发的电迁移失效分析

电迁移是半导体器件常见的失效机理,可以导致金属的桥连或者产生空洞,引起短路或者开路等互连失效.总结了两种典型的电迁移失效模式:热电迁移和电化学迁移,阐述了两种电迁移的失效应力诱发条件,以及失效分析方法.通过失效分析案例研究,加深对两种失效机理的认识并提供电迁移失效分析的基本思路.     

金属电迁移测试过程中的电介质击穿效应

金属互连电迁移有断路失效和短路失效两种常规失效模式,其中短路失效是由于发生了析出效应.目前对电迁移断路失效的研究较多,但是对于析出效应(短路失效)的研究较少.研究发现在金属电迁移析出效应监测过程中易产生两种电介质击穿效应,分别为在实验刚开始发生的瞬时电介质击穿(TZDB)效应和测试过程中产生的时间依赖性电介质击穿(TDDB)效应.此外,电介质层材料的介电常数值越高,其耐电介质击穿的能力越高.析出效应的监测电场强度的设定值应该同时考虑电介质层材料与测试结构的特性,监测电场强度的设定范围建议为0.15～0.24 MV/cm,以防止在析出效应监测过程中发生电介质击穿,混淆两种不同的失效机理,造成误判.     

改进的电迁移独立失效元模型

当前被广泛采用的描述电迁移失效的独立失效元模型存在很多缺陷．本文根据电迁移失效的物理机制和一些必要的假设，对其进行了一些改进．主要是以三叉点代替晶粒作为独立失效元，并不再假设单个失效元的中值失效时间与晶粒大小无关．对连线宽度、晶粒大小与电迁移寿命的模拟结果都比传统的独立失效元模型更符合实验事实．     

倒装芯片互连结构中电流聚集研究

由于电流聚集,在倒装芯片封装技术中,电迁移已经成为一个关键的可靠性问题。分析了电迁移力和电迁移中值失效时间,采用二维模型研究了电流密度和焦耳热在倒装芯片互连结构中的分布以及影响电流密度和焦耳热分布的因素。结果表明铝线(Al)和凸点下金属层(UBM)的厚度对电流密度和焦耳热分布有很大的影响。     

失效物理

集成电路互连电迁移失效模拟软件(见9905150)VM-1中频调制器的分析与维修(见9904700)采用分段线性电路技术的电阻短路的故障特性(见9904662)     

铜互连电迁移失效的研究与进展

Cu/低k互连的电迁移失效与互连材料、工艺、结构和测试条件都有着密切的联系。论述了近年来铜互连电迁移可靠性的研究进展,讨论了电迁移的基本原理、失效现象及其相关机制和微效应以及主导失效的机制——界面扩散等,同时探讨了改善铜互连电迁移性能的各种方法,主要有铜合金、增加金属覆盖层及等离子体表面处理等方法,并指出了Cu互连电迁移可靠性研究有待解决的问题。     

无铅焊料的研究（4）——电迁移效应

电迁移是金属原子沿着电流方向的移动。阐述了无铅焊料中电迁移的物理特性,由于焊点的特殊几何形状,电流拥挤效应将发生在焊点与导线的接点处;电迁移效应导致无铅焊料中金属间化合物(IMC)的生成与溶解,以及焊点下的金属化层(UBM)的溶解和消耗,使原子发生迁移并会产生孔洞,造成焊点破坏,缩短了焊点平均失效时间(MTTF),从而带来可靠性问题。     

45nm双大马士革Cu互连逆流电迁移双峰现象及改善

集成电路中金属连线的逆流电迁移(EM)的双峰失效现象在45 nm双大马士革低k材料铜布线工艺中变得尤为突出,介绍了由于空洞存在于连接电路导致电迁移的早期失效,总结出两个早期失效的主要原理:分别是空洞形成在通孔以及浅槽与通孔的斜面,这是由于淀积扩散阻挡层和铜工艺在上述两个地方存在弱点,越薄的扩散阻挡层厚度对EM越不利。因为偏薄的扩散阻挡层不利于阻挡铜扩散,尤其在通孔的侧壁和边角斜面,这样在测试电迁移的高温大电流下,铜在通孔侧壁和边角斜面处易扩散而形成空洞,最终导致芯片失效。实验表明可以通过优化双大马士革结构通孔以及浅槽与通孔的斜面的长宽比(AR)减少消除这些弱点。介质层(ILD)的厚度,浅槽的深度以及通孔的关键尺寸可以作为调节AR的主要方法。     

Noise and reliability in simulated thin metal films

Many macroscopic aspects of electromigration damage in thin metal films have been investigated by means of Monte Carlo simulations based on simplified physical model. The employed model, can be described as a middle-scale model, in which the physical system is modeled with a high level of abstraction, without a detailed atomic physical model of the system.Among the many effects of the electromigration phenomenon, the simulator has been used to investigate several statistical properties of electromigration failure and the noise behaviour.Notwithstanding this simplicity, it is able to generate results in good agreement with many experimental observations: the lognormal distribution of failures, dependence of the mean time to failure from stress current and film geometry, Black exponent, noise statistics.Furthermore, this simulations confirmed a significant correlation between electromigration noise in the initial phase of stress and time to failure which has been suggested by a few experimentalists. This correlation can be usefully exploited as an early indication of the onset of electromigration damage on a per-sample basis.     

Electromigration—A brief survey and some recent results

Recently, electromigration has been identified as a potential wear-out failure mode for semiconductor devices employing metal film conductors of inadequate cross-sectional area. A brief survey of electromigration indicates that although the effect has been known for several decades, a great deal of the processes involved is still unknown, especially for complex metals and solute ions. Earlier design equations are improved to account for conductor film cross-sectional area as well as film structure, film temperature, and current density. Design curves are presented which permit the construction of high reliability "infinite life" aluminum conductors for specific conditions of maximum current and temperature stress expected in use. It is also shown that positive gradients, in terms of electron flow, of temperature, current density, or ion diffusion coefficient foreshorten conductor life because they present regions where vacancies condense to form voids.     

The influence of TiN ARC thickness on stress-induced void formationin tungsten-plug vias

This paper describes a new failure mechanism in W-plug vias, and the process conditions which enhance it. For submicron technologies, the limiting factor in interconnect reliability performance is increasingly dominated by the electromigration resistance of tungsten-plug vias. We have observed that under certain experimental conditions, early electromigration failures can be induced in via-chain test structures. We have demonstrated that these are caused by stress-induced void formation in the metal line immediately beneath the tungsten plug. This is thought to be due to highly localized film stress around the base of the plug, which can be minimized by increasing the thickness of the TiN anti-reflective coating (ARC). This has the effect of reducing the incidence of early failure by suppressing the stress-induced failures     

热应力条件下VLSI金属化布线的可靠性

利用深层掩埋Ｔｉ－Ｗ自加热结构产生了沿金属化条长方向的温度梯度，通过电阻测温法精确测定实验条上的温度分布，从电迁徙平均失效时间、ＳＥＭ分析等角度，研究了温度梯度对电迁徙的影响。实验发现，选择合适的工艺条件可保证电阻测温法的稳定性；温度梯度的不同取向对电迁徙平均失效时间存在较大影响，逆向温度梯度可极大地提高金属化的抗电迁徙寿命。     

Monte Carlo simulation for improving electromigration lifetime by balancing temperature and structural gradients

It has been established that the prime cause for electromigration damage in metallisation lines is the ionic flux divergence, which is mainly associated with temperature and microstructural gradients along the lines. Monte Carlo simulation for electromigration failure has been performed using a model including the above effects. The median time to failure is found to be increased about 100% by employing an imposed grain size distribution to balance the influence of temperature variations. This work demonstrates the possibility and importance of film microstructural control in the presence of a temperature gradient for metallisation reliability improvement.     

A precise method to determine the stress current to be applied to electromigration test structures

The density of the stress current flowing through metal stripes for electromigration (EM) median time to failure (MTF) tests should vary as little as possible among all the structures under test. This paper proposes an alternative method to the procedure described in ASTM F 1260, to determine the stress currents for these tests, resulting in smaller stress current density differences among different test structures. This method uses the average resistivity of the metal film to calculate the stress current for each individual test structure. In the standard method (ASTM F 1260), the average film thickness is used to calculate the cross-sectional area, which is used to calculate the stress current. The resistivity of the deposited film (almost always) varies less over a wafer than the film thickness. The alternative method results in an improved precision of the stress current density. A comparison between the two methods is made and two experiments are used to illustrate the difference. For Al-1at.% Si layers deposited in our sputtering system, the precision of the stress current density is improved by a factor of three.     

Physically based models of electromigration: From Black’s equation to modern TCAD models

Electromigration failure is a major reliability concern for integrated circuits. The continuous shrinking of metal line dimensions together with the interconnect structure arranged in many levels of wiring with thousands of interlevel connections, such as vias, make the metallization structure more susceptible to failure. Mathematical modeling of electromigration has become an important tool for understanding the electromigration failure mechanisms. Therefore, in this work we review several electromigration models which have been proposed over the years. Starting from the early derivation of Black’s equation, we present the development of the models in a somewhat chronological order, until the recent developments for fully three-dimensional simulation models. We focus on the most well known, continuum physically based models which have been suitable for comprehensive TCAD analysis.     

Copper interconnect electromigration behaviors in various structures and lifetime improvement by cap/dielectric interface treatment

Copper interconnect electromigration performance was examined in various structures and three low-k materials (k = 2.65–3.6) using advanced BEOL technology. Strong current dependence effect on electromigration lifetime in three levels via terminated metal lines structure was shown. Moreover, different process approach will lead to different EM behavior and related failure mode. Multi-modality electromigration behavior of Cu dual damascene interconnects were studied. Both Superposition and Weak-Link models were used for statistical determination of lifetimes of each failure models (Statistical method). Results were correlated to the lifetimes of respective failure models physically identified according to resistance time evolution behaviors (Physical method). Good agreement was achieved. Various testing structures are designed to identify the EM failure modes. Extensive failure analysis was carried out to understand the failure phenomena of various test structures. The activation energies of failure modes were calculated. The weak links of interconnect system were also identified. A significant improvement of electromigration (EM) lifetime is achieved by modification of the pre-clean step before cap-layer deposition and by changing Cu cap/dielectric materials. A possible mechanism for EM lifetime enhancement was proposed. Cu-silicide formation before cap-layer deposition and adhesion of Cu/cap interface were found to be critical factors in controlling Cu electromigration reliability. The adhesion of the Cu/cap interface can be directly correlated to electromigration MTF and activation energy. Results of present study suggest that interface of Cu interconnects is the key factor for EM performance for advanced BEOL technology design rules.     

An introduction to Cu electromigration

Electromigration is a major reliability concern in today’s integrated circuits due to the aggressive scaling of interconnect dimensions and the ever-increasing current densities at operation. In addition, the recent introduction of new materials and processing schemes lead to even more challenges in guaranteeing interconnect robustness against electromigration failure. In this article, we review basic electromigration physics in which the main differences between Al- and Cu-based interconnects relevant to electromigration are covered. We also discuss recent process-related advances in electromigration reliability such as the use of alloys and metal caps. Next, the impact of low-k inter-level dielectrics (ILD) on electromigration performance is addressed. Finally, the methodology of electromigration lifetime extrapolation, including reliability assessments of more complex interconnect geometries, is covered.