双极型装控晶体管模型及原理

本文提出一种新的双极型压控晶体管模型，并说明其工作原理。这种器件有两种载流子参与导电，有较大的电流密度和功率，导电能力又受电压控制，具有较大的输入阻抗，兼有双极器件和ＭＯＳ场效应器件的特点。     

新型双注入结型场效应器件

本文提出一种新型双注入结型场效应晶体管（BJFET）器件构思，并说明其工作原理。这种器件兼有双极型器件和结型场效应器件的特点，即有两种载流子参与导电，导电能力受电压控制，具有较大的电流容量和输入电阻。     

SOI横向栅控双极晶体管特性研究

横向SOI双极技术具有工艺简单、寄生电容小等优势,被认为是射频领域最有希望的技术之一。为了得到可用于射频领域的SOI横向栅控双极晶体管特性,采用一种SOI横向栅控双极晶体管器件结构,研究范围包括工艺实现过程和器件性能特性。实验表明,该器件工艺与平面CMOS工艺完全兼容,通过对栅端电压的控制,可以实现hFE在一个较大的范围内自由调节,具有更大的使用灵活性。     

GNRFET双极特性及工作区域研究

石墨烯器件作为下一代纳米电子器件的有力竞争者受到广泛关注,但对其器件工作机理的研究尚不透彻。对石墨烯纳米带场效应晶体管(graphene nanoribbon field effect transistor,GNRFET)的双极特性进行了研究,分析了偏置电压对GNRFET转移特性和输出特性的影响,发现除已被关注到的栅电压外,源漏电压对GNRFET的双极特性亦有作用,并将两者综合考虑才能全面反映GNRFET的工作状态。在此基础上,进一步提出了工作区域的概念,将GNR-FET的工作区域划分为空穴导电区、电子导电区、转变区和截止区,为GNRFET器件的应用和电路设计提供指导。     

基于SOI的双极场效应晶体管

在分析了双极型晶体管和场效应晶体管各自的特点和不足后，介绍了一种既具有双极型晶体管较大电流容量和功率输出，又具有场效应晶体管高输入阻抗的电子器件——双极MOS场效应晶体管(BJMOSFET)，同时指出体硅BJMOSFET的阳极扩散区与衬底之间存在较大的漏电流，可产生较大的寄生效应。提出了一种新型固体电子器件——基于SOI的BJMOSFET，分析了其工作原理j与体硅BJMOSFET比较，由于SOI技术完整的介质隔离避免了体硅器件中存在的大部分寄生效应，使基于SOI的BJMOSFET在体效应、热载流子效应、寄生电容、短沟道效应和闩锁效应等方面具有更优良的特性。     

宽温高频高反压沟道项区晶体管研制

耗尽是基区双极晶体管也称为双极静电感应晶体管（ＢＳＩＴ），基电流放大系数（ｈＦＥ）具有负的温度系数。双极结型晶体管（ＢＪＴ）的ｈＦＥ具有正的温度系数，将ＢＳＩＴ与ＢＪＴ并联，采用ＢＪＴ常规平面工艺制造了宽温高频高反压沟道基区双极ＰＮＲ晶体管。本文描述了这种瓣器件结构、工作原理、设计与制造。新器件突出特点是：当温度变化较大时，ｈＦＥ漂移较小。测试结果表明：环境温度从２５℃升到１８０℃时，器件的ｈＦＥ     

SOI横向双晶体管结构研究

本文首先概括地介绍了体硅、SOI纵向双极晶体管和横向双极晶体管的各自特点，并简要地阐述了SOI横向双极晶体管的发展；其次，对各种SOI横向双极晶体管的结构与性能进行了分析研究；最后，我们认为SOI横向双极晶体管是一种比较理想的双极器件，不失为SOI／BiCMOS的理想选择。     

MOS—双极功率半导体技术的进展

对曾经推动MOS栅控型新型功率晶体管工艺发展的一些新技术作了评述。这种器件技术的优点是有很高的输入阻抗而可用低成本集成电路控制这种器件。描述了这类器件中的两种类型——功率MOSFET和MOS-双极器件——运行的物理过程。分析了加工工艺和器件额定性能的发展趋势。由于这些器件性能优越,可望在未来完全取代功率双极晶体管。     

扫描电镜在LCD导电金球连接性能失效分析中的应用

导电金球的压缩变形程度与连接LCD器件上下ITO电极的导电性能密切相关．对直径5-8μm的导电金球的压缩变形情况进行微观形貌分析及精确的测量是必要的。在对LCD器件进行导电金球连接性能失效分析方面,首次提出采用扫描电镜进行剖面微观形貌分析及测量的方法,由此可以较精确地计算出导电金球的压缩变形程度,解决了普通光学检测仪器微观检测精度不足的问题。实践证明．该方法在进行导电金球连接性能失效分析及LCD器件的可靠性设计及验证方面有较大的帮助。     

硅低温双极晶体管的数值模拟

本文讨论了有关低温双极器件模拟物理的数的低温模型和各种低温物理效应，确立了适用于低温双极器件模拟的数值分析方法，建立了适用于７７－３００Ｋ温度范围内硅双极器件模拟程序，最后模拟分析了一典型结构晶体管的常温和低温时的工作特性。     

Thin film ZnS:Mn AC-electroluminescent device with a Ge layer

A new thin film electroluminescent device (indium tin oxide ITO-Y2O3- (ZnS:Mn)- Ge-Y2O3- Al) (type II) has been prepared, and is compared to the conventional structure (ITO- Y2O3- (ZnS:Mn) - Y2O3- Al) (type I). The optically active conduction charge is measured for both types in order to ascertain the effect of the Ge layer which is believed to act as a carrier injection source. We found that in this new structure, compared to type I, the amount of the conduction charge is larger, but the maximum luminance value is lowered by a factor of 2 to 3 and the breakdown voltage is slightly lowered. These results can be explained from the experimental observation that remarkable assymmetry of luminescence waveforms is present in the type II device, i.e., the Ge layer influences the electric field near the ZnS-Ge interface. The appearance of the type II display is improved compared to type I.     

掺杂浓度对槽栅nMOSFET特性的影响研究

讨论了槽栅结构nMOSFET的掺杂浓度对器件特性的影响，并通过二维器件仿真程序PISCES—Ⅱ进行了计算模拟比较。结果表明，提高衬底掺杂浓度，能使源漏区与沟道之间的拐角效应增大，对热载流子效应抑制的作用明显；提高沟道掺杂浓度，能减小沟道电荷的调制效应，使阈值电压更好。调节沟道掺杂浓度比调节衬底掺杂浓度对器件的影响更大。     

衬底偏压对硅基高压器件新结构击穿电压特性的影响

提出基于衬底偏压技术的double RESURF结构,称为Sb double RESURF LDMOS。在n型衬底和n型漂移区之间嵌入p型外延层,阻挡器件阻断状态下的纵向电流通路,改变体内电场分布。衬底偏压加强漂移区电荷共享效应,降低漏极下方纵向电场峰,该技术对提高薄漂移区横向功率器件的纵向击穿电压尤其重要。结果表明,在保持较小导通电阻下,该结构较常规LDMOS击穿电压提高97%。     

具有L型栅极场板的双槽双栅绝缘体上硅器件新结构

为了降低绝缘体上硅（SOI）功率器件的比导通电阻,同时提高击穿电压,利用场板（FP）技术,提出了一种具有L型栅极场板的双槽双栅SOI器件新结构.在双槽结构的基础上,在氧化槽中形成第二栅极,并延伸形成L型栅极场板.漂移区引入的氧化槽折叠了漂移区长度,提高了击穿电压;对称的双栅结构形成双导电沟道,加宽了电流纵向传输面积,使比导通电阻显著降低;L型场板对漂移区电场进行重塑,使漂移区浓度大幅度增加,比导通电阻进一步降低.仿真结果表明：在保证最高优值条件下,相比传统SOI结构,器件尺寸相同时,新结构的击穿电压提高了123%,比导通电阻降低了32%;击穿电压相同时,新结构的比导通电阻降低了87.5%;相比双槽SOI结构,器件尺寸相同时,新结构不仅保持了双槽结构的高压特性,而且比导通电阻降低了46%.     

激光-熔化极脉冲电弧复合焊接的双重导电机制

对激光-电弧复合焊接的稳弧机理始终存在不同的观点。通过高速摄像机和光谱分析仪对比研究了激光与电弧复合前后电弧形态发生的变化。研究发现复合后电弧呈现一种全新的形态,具有两个独立的导电通道,这种现象被称为"双重导电机制"。这种机制对维持电弧稳定和保证焊缝成型良好具有非常重要的意义,正是激光-电弧复合焊接高速焊接过程中稳弧的关键所在。研究还发现"双重导电机制"的建立过程存在时间顺序,辅助导电通道首先是从激光小孔周围建立起来,然后逐渐扩展到整个电弧区域。各种焊接参数对"双重导电机制"也存在明显的影响。     

一种新的Halo掺杂圆柱围栅MOSFET阈值电压解析模型

通过在圆柱坐标系中精确求解泊松方程,建立了全新的Halo掺杂圆柱围栅MOSFET静电势,电场以及阈值电压的解析模型。与采用抛物线电势近似法得到的解析模型相比,当沟道半径远大于氧化层厚度时,新模型更为精确。模型还考虑了Halo区掺杂浓度、氧化层厚度以及沟道半径对器件阈值电压特性的影响。结果表明,采用中等程度的halo区掺杂浓度、较薄的栅氧化层以及较小的沟道半径可以有效改善器件的阈值电压特性。解析模型与三维数值模拟软件ISE所得结果高度吻合。     

Carrier transport mechanism in aluminum nanoparticle embedded AlQ3 structures for organic bistable memory devices

Electrical bistability is demonstrated in organic memory devices based on tris-(8-hydroxyquinoline)aluminum (AlQ₃) and aluminum nanoparticles. The role of the thickness of middle aluminum layer and the size of the nanoparticles in device performance is investigated. Above a threshold voltage, the device suddenly switches from a low conductivity OFF state to a high conductivity ON state with a conductivity difference of several orders of magnitude. The OFF state of the device could be recovered by applying a relatively high voltage pulse. The electronic transition is attributed to an electric field induced transfer of charge between aluminum nanoparticles and AlQ_3. The type of charge carriers responsible for conductance switching is investigated. The charge carrier conduction mechanism through the device in ON and OFF states is studied by temperature dependent current–voltage characteristics and analyzed in the framework of existing theoretical models. The conduction mechanism in the OFF state is dominated by field-enhanced thermal excitation of charge carriers from localized centers, whereas it changes to Fowler–Nordheim tunneling of charge carriers in the ON state. The device exhibited excellent stability in either conductivity states. The results indicate the strong potential of the device towards its application as a nonvolatile electronic memory.     

Carrier Transport Mechanism in a Nanoparticle-Incorporated Organic Bistable Memory Device

In this letter, the conduction mechanism in nanoparticle-contained polymer memory was investigated experimentally and theoretically. The current-voltage characteristics showed that the device switches from an initial low-conductivity state to a high-conductivity state upon application of an external electric field at room temperature. The current transition exhibited a very narrow voltage range that causes an abrupt increase of current. A trap-filled space-charge-limited current model was proposed and supported by the experimental data to explain the transport mechanism in organic memory.     

A novel partial-SOI LDMOSFET (>800 V) with n-type floating buried layer in substrate

In this paper, a novel high voltage lateral double diffused metal–oxide–semiconductor (LDMOS) field effect transistor based on partial silicon-on-insulator (PSOI) technology is proposed and investigated based on the numerical simulations. The structure is characterized by an n-type floating buried layer (NFBL) in the substrate under the silicon window near the drain. The buried layer in the substrate modulates the lateral and vertical electric field, which results in the electric field of the drift region distributed uniformly. Therefore, the breakdown voltage (BV) of the device is significantly improved. The influences of the key parameters on device performance of the proposed structure are discussed. Moreover, the self-heating effect (SHE) is greatly alleviated duo to the silicon window helps thermal conduction to the substrate, which improved the reliability of device application.