晶圆尺寸级封装器件的热应力及翘曲变形

晶圆尺寸级封装(WLCSP)器件的尺寸参数和材料参数都会对其可靠性产生影响。使用有限元分析软件MSCMarc,对EPS/APTOS生产的WLCSP器件在热循环条件下的热应力及翘曲变形情况进行了模拟,分析了器件中各个尺寸参数对其热应力及翘曲变形的影响。结果表明:芯片厚度、PCB厚度、BCB厚度和上焊盘高度对WLCSP的热应力影响较为明显。其中,当芯片厚度由0.25mm增加到0.60mm时,热应力增加了21.60MPa;WLCSP的翘曲变形主要受PCB厚度的影响,当PCB厚度由1.0mm增加到1.60mm时,最大翘曲量降低了20%。     

WLCSP焊球直径对其剪切强度和失效模式的影响

为满足电子设备不断小型化与多功能化的需要,圆片级芯片尺寸封装(WLCSP)芯片上焊球的尺寸不断缩小,焊球直径达100 μm.选用100,150,200,250和300 μm SAC (Sn-Ag-Cu)5种不同尺寸焊球的WLCSP芯片样品,经历相同的回流历程,对不同尺寸单个焊球进行剪切实验,从而得到焊球剪切强度和失效模式,抛光截面并测量了焊球金属间化合物(IMC)层的厚度.研究发现,随着焊球直径减小,IMC层厚度呈线性下降,经过回流历程后,IMC厚度随焊球直径增大而增厚,过薄和过厚的IMC层都减弱焊球剪切强度.经过回流后,界面断裂成为主要的断裂模式.     

FeNi合金UBM圆片级封装焊点剪切力研究

FeNi合金与无铅焊料反应速率低,生成的金属间化合物(IMC)较薄,有望作为圆片级封装(WLP)凸点下金属(UBM)层材料.对两种FeNi UBM以及一种Cu UBM圆片级封装样品进行回流、湿热以及预处理实验,并通过推球的方法,对其焊点进行剪切测试.通过断面与截面分析,研究其在不同处理条件下的金属间化合物生长情况,分析其断裂模式.结果表明,FeNi UBM焊点剪切力高于Cu UBM.Fe47Ni UBM与焊料反应生成的金属间化合物较薄,对于剪切力影响较小,而Fe64Ni UBM与焊料反应生成离散的CuNiSn金属间化合物,对于其焊点强度有提高作用,Cu UBM与焊料反应生成较厚的金属间化合物,会明显降低焊点的剪切力.断面分析表明,Cu UBM会随焊球发生断裂,其强度明显小于FeNi UBM.     

铝/镍/铜UBM厚度对SnAgCu焊点的力学性能及形貌影响

研究了倒装芯片中UBM制备和焊球回流工艺流程。通过改变阻挡层Ni和浸润层Cu的厚度,结合推拉力测试实验,探究了SnAgCu焊点剪切强度的变化规律。研究结果表明,UBM中阻挡层Ni对SnAgCu焊点的力学性能影响最大,而浸润层Cu厚度的增加也能提高SnAgCu焊点的力学性能。进一步对推拉力实验后的焊点形貌进行了SEM观察和EDS分析,得到了焊盘剥离、脆性断裂、焊球剥离、韧性断裂四种不同的焊点失效形式,代表着不同的回流质量,而回流质量主要由UBM的成分和厚度决定。研究结果为倒装焊工艺的优化提供了理论指导。     

Sn0.7Cu无铅焊点的电迁移失效模拟及优化分析

基于ANSYS有限元软件,综合考虑电子风力、温度梯度、应力梯度和原子密度梯度四种电迁移驱动机制,采用原子密度积分法(ADI)对倒装芯片球栅阵列封装(FCBGA)的Sn0.7Cu无铅焊点进行电迁移失效模拟。针对焊点直径、焊点高度、焊点下金属层(UBM)厚度三个关键参数进行电迁移失效的正交试验优化,探究焊点尺寸对电迁移失效的影响。研究表明:焊点直径和高度的增加会缩短焊点的电迁移失效寿命(TTF),而UBM层厚度对焊点失效寿命的影响相对较小;焊点局部拉应力对焊点的失效寿命影响较大,通常会加剧焊点的空洞失效。     

化学镍金UBM沉积差异探讨

UBM（under bumping metallization凸点下金属）的制作是整个FlipChip和WLCSP封装工艺中的关键。化学镍金UBM技术以其成本低、可靠性高而受到越来越多的关注和应用。对于不同功能和大小的I／O金属电极,化学镍金UBM的沉积会出现差异和不同。文中用混合电位理论解释了半导体晶圆化学镍金UBM沉积差异的现象。搅拌因素对于面积大小不同的I／O电极混合电位的影响是不同的,面积小的I／O电极其UBM沉积速度高于面积大的I／O电极。不同功能的I／O电极有着不同的起始电势,从而影响I／O电极的混合电位,表现为最终UBM沉积厚度和表面形貌的差异。     

一种低损耗毫米波垂直互联设计

设计了一种利用球栅阵列(BGA)的毫米波垂直互联,解决了毫米波系统三维(3D)集成时层间信号互联的低损耗传输问题.根据传输线理论,利用电磁仿真软件对这种采用BGA的垂直互联进行了仿真,并对层间通孔半径、焊球半径、焊盘半径等对传输性能的影响进行了分析.样件测试结果显示,在28.4~30.4 GHz,其层间垂直传输损耗小于0.36 dB,反射小于-15 dB.该垂直互联结构简单、性能良好,可广泛用于毫米波微系统3D集成.     

芯片倒装封装中焊球及铜互连对高速差分信号传输特性影响的仿真研究

焊球与铜互连是芯片倒装封装中两种主要的互连结构,而随着数字电路时钟频率的不断提升,差分信号已成为高速数字电路中最常用的信号形式。采用HFSS全波仿真方法对芯片倒装封装中高速差分信号在差分对焊球和铜互连结构中的传输特性进行了研究。首先在理想情况下对差分对焊球结构进行了建模,分析了焊球阵列中焊球的尺寸和节距参数对差分信号传输特性的影响,发现在假定焊球节距为焊球直径2倍的情况下,现阶段常用的直径为0.1~1.27 mm的焊球中焊球尺寸和节距越小越能在宽频段内实现更好的传输性能。其次对平行式和内弯式、外弯式非平行差分铜互连结构进行了对比研究,发现平行式结构优于内弯式非平行结构,内弯式非平行结构优于外弯式非平行结构。     

硅微机械陀螺仪封装应力研究

封装热应力会降低硅微机械陀螺仪性能,为了减小封装热应力,对封装热应力与封装材料之间的关系进行了研究.首先对封装的硅微机械陀螺仪结构进行了简化,建立了有限元模型,仿真并分析了在封装过程中陶瓷基底材料和粘接剂对热应力的影响.仿真结果表明,陶瓷基底和粘接剂的热膨胀系数与硅的热膨胀系数匹配,且粘接剂的杨氏模量较小时,热应力较小.粘接层厚度超过60μm,平面尺寸大于陀螺仪芯片尺寸时,热应力较小.     

硅通孔尺寸与材料对热应力的影响

通过有限元分析研究了单个硅通孔及两片芯片堆叠模型的热应力。采用单个硅通孔模型证实了应力分布受填充材料(铜,钨)的影响,提出钨在热应力方面的优越性,确定了硅通孔尺寸(通孔直径、深宽比等因素)与热应力大小间的对应关系。为寻找拥有最佳热应力的材料组合,采用两片芯片堆叠的二维模型,对常用材料的组合进行了仿真分析,发现以二氧化硅为隔离层,钨为填充金属,锡为键合层的模型具有最理想的热应力特性,此外,铜、ABF以及锡的组合也表现出良好的热应力特性。     

Characterization of the Effect of Shape Memory Alloy on Solder Joint Strength Through Modeling and Testing

Currently some of the most common problems that surface mount technology encounters are warpage, delamination, and inelastic strain concentration accumulated in the solder joint during thermal cycling because of mismatch of thermal expansion coefficient between the package and chip side. Material as well as package structure are the critical issues with respect to these problems. The objective of this research is to investigate how shape memory alloy (SMA) applied in the under bump metallization (UBM) can affect solder joint reliability under thermal mechanical stress. Joint strength tests revealed the better strength of solder joints with SMA UBM after accelerated thermal cycling test. Finite element modeling as well as multilayer stress calculations revealed less strain accumulated in the solder and more stress concentrated in Si in the solder joint with SMA UBM. A mechanism by which the SMA accommodates most of the stress and strain caused by the mismatch of the thermal expansion coefficients was proposed to explain the reinforcement of the solder joint by the SMA UBM.     

Design and optimization of thermo-mechanical reliability in wafer level packaging

In this paper, a variety of wafer level packaging (WLP) structures, including both fan-in and fan-out WLPs, are investigated for solder joint thermo-mechanical reliability performance, from a structural design point of view. The effects of redistribution layer (RDL), bump structural design/material selection, polymer-cored ball application, and PCB design/material selection are studied. The investigation focuses on four different WLP technologies: standard WLP (ball on I/O WLP), ball on polymer WLP without under bump metallurgy (UBM) layer, ball on polymer WLP with UBM layer, and encapsulated copper post WLP. Ball on I/O WLP, in which solder balls are directly attached to the metal pads on silicon wafer, is used as a benchmark for the analysis. 3-D finite element modeling is performed to investigate the effects of WLP structures, UBM layer, polymer film material properties (in ball on polymer WLP), and encapsulated epoxy material properties (in copper post WLP). Both ball on polymer and copper post WLPs have shown great reliability improvement in thermal cycling. For ball on polymer WLP structures, polymer film between silicon and solder balls creates a ‘cushion’ effect to reduce the stresses in solder joints. Such cushion effect can be achieved either by an extremely compliant film or a ‘hard’ film with a large coefficient of thermal expansion. Encapsulated copper post WLP shows the best thermo-mechanical performance among the four WLP structures. Furthermore, for a fan-out WLP, it has been found that the critical solder balls are the outermost solder balls under die-area, where the maximum thermal mismatch takes place. In a fan-out WLP package, chip size, other than package size, determines the limit of solder joint reliability. This paper also discusses the polymer-cored solder ball applications to enhance thermo-mechanical reliability of solder joints. Finally, both experimental and finite element analysis have demonstrated that making corner balls non-electrically connected can greatly improve the WLP thermo-mechanical reliability.     

Reliability evaluations of under bump metallurgy in two soldersystems

Under bump metallurgy (UBM) reliability is one of the critical issues in the total reliability of a flip-chip bumping technology. Since the UBM materials and structures vary for different bumping technologies, the UBM strength and reliability need to be determined for each design and process. In addition, the stress that a UBM experiences during thermal cycles depends on the solder alloy used in the interconnect. Different solder alloys require different UBM structures and strengths to achieve good reliability in thermal cycling. In this study, a simplified stress model is developed to determine the UBM stress during thermal cycling. A simplified stress model for the UBM strength is also developed. These models are used to predict the stress and strength of the UBM under the die pull test and the thermal cycle conditions for both eutectic and high lead solder systems. A methodology for using the pull test results to evaluate UBM reliability is also discussed. This methodology can be extended to the studies of UBM's with other solder systems such as lead free solder systems     

Influence of Intermetallic Properties on Reliability of Lead-Free Flip-Chip Solder Joints

Electroplated pure tin bumping as a lead-free alternative for ultra fine pitch applications is a relatively easy process and has provided us with comparable results to eutectic Sn/Pb for thermal cycling reliability. Experimentally, it has been reported that a significantly higher (~40%) thermal cycle fatigue life is seen with the use of cobalt under bump metallization (UBM) instead of copper UBM for a flip-chip device assembled on an alumina substrate. In the current approaches used to estimate fatigue life of solder joints, the solder joint is treated as a homogenous material and modeled as such. However, the smaller joint sizes and higher reactivity of Sn implies that a larger amount of intermetallics are formed as a percentage of bump volume. The existing approach cannot account for the influence on the fatigue behavior of these intermetallic layers within the solder joint. In order to investigate if a simplified engineering approach can provide some insight into this issue, we have attempted to explicitly model the intermetallics as a continuous but separate part of the solder joint. The main damage parameter investigated is the accumulated inelastic strain in a single thermal cycle. From the results, it is clear that the Young's modulus of the intermetallic layer plays an important role, more so when the ratio of intermetallic thickness to the solder joint standoff increases. Thickness of the intermetallic layer also influences the overall strain accumulation in the same manner. The CTE of the intermetallic layer has a relatively lesser influence on the strain accumulation. Both the experimental and FE results suggest that changing the UBM from copper to cobalt can improve the fatigue life by 20%-30%.     

基于正交试验设计的塑封球栅阵列器件焊点工艺参数与可靠性关系研究

基于正交试验设计法对塑封球栅阵列(PBGA)器件焊点工艺参数与可靠性关系进行了研究.采用混合水平正交表L₁₈(2×3⁷)设计了18种不同工艺参数组合的PBGA测试样件,进行了546小时、最大循环周数2140周的PBGA测试样件可靠性加速热循环试验.基于试验结果进行了极差分析和方差分析;研究了PBGA测试样件寿命的威布尔分布;采用有限元分析方法对热循环加载条件下PBGA焊点内应力应变分布进行了研究.试验结果表明失效焊点裂纹出现于焊点与芯片基板的交界面上.研究结果表明:样件规格对PBGA焊点可靠性有高度显著影响,芯片配重对PBGA焊点可靠性有显著的影响,焊盘直径和钢网厚度对PBGA焊点可靠性无显著影响;最优工艺参数组合为:S2D2G2M1和S2D2G2M2.有限元分析表明在热循环加载条件下PBGA器件内应力最大区域位于焊点与芯片基板的接触面上,裂纹首先在焊点与芯片基板的接触面处产生,有限元分析结果与试验结果相吻合.     

基于再流焊冷却过程应力分析的板极组件BGA焊点参数优化

建立了板级组件BGA（Ball Grid Array）焊点有限元分析模型,对BGA焊点进行了再流焊冷却过程应力仿真分析,设计并完成了验证性实验以验证仿真分析方法的有效性,分析了焊点结构参数和材料变化对焊点再流焊冷却过程应力应变的影响,采用响应面法建立了焊点应力与结构参数的回归方程,结合遗传算法对焊点结构参数进行了优化.结果表明：实验结果证明了仿真分析的有效性;焊点应力随着焊点高度的增加而增大,随着焊点直径的增加而减小;最优焊点结构参数水平组合为：焊点高度0.44mm、焊点直径0.65mm、焊盘直径0.52mm和焊点间距1.10mm;对该最优焊点仿真验证表明最大应力下降了0.1101MPa.     

球栅阵列封装中SnPb焊点的应力应变分析

基于SnPb焊料的统一粘塑性Anand本构模型,运用ANSYS有限元软件分析了球栅阵列封装中复合SnPb焊点在热循环过程中的应力、应变的分布,观察到SnPb焊料的蠕变行为和应力松弛现象,结果证明:外侧焊点经受的应力、应变范围比内侧焊点大;焊点的最高应力区域出现在Sn60Pb40焊料的最外缘处,最高应变区域出现在Pb90Sn10焊料与UBM层接触面的最上缘处.     

A reliability comparison of electroplated and stencil printed flip-chip solder bumps based on UBM related intermetallic compound growth properties

The effects of under bump metallurgy (UBM) microstructures on the intermetallic compound (IMC) growth of electroplated and stencil printed eutectic Sn-Pb solder bumps were investigated. The process parameters and their effects on UBM surface morphology and UBM shear strength were studied. For the electroplating process, the plating current density was the dominant factor to control the Cu UBM microstructure. For the stencil printing process, the zincation process has the most significant effect on the Ni UBM surface roughness and Ni grain sizes. In both processes, the good adhesion of UBM to aluminum can be obtained under suitable UBM processing conditions. Samples with different UBM microstructures were prepared using the two processes. The resulting samples were thermal aged at 85/spl deg/C, 120/spl deg/C, and 150/spl deg/C. It was observed that the Cu UBM surface roughness had larger effect on the IMC growth and solder ball shear strength than the Ni UBM surface roughness. The thickness of Cu/sub 3/Sn and Cu/sub 6/Sn/sub 5/ IMC depended strongly on the UBM microstructure. However, for Ni/Au UBM, no significant dependence was observed. More likely, the thickness of Au-Ni-Sn IMC near the IMC/solder interface was controlled by the amount of gold and the gold diffusion rate in the solder. Shear tests were performed after thermal aging tests and thermal/humidity tests. Different failure modes of different sample groups were analyzed. Electroless Ni UBM has been developed because it is a mask-less, low-cost process compared to electroplated Cu UBM. This study demonstrated that the process control was much easier for Ni UBM due to its lower reactivity with Sn material. These properties made Ni UBM a promising candidate for the lead-free solder applications.     

The influence of Sn–Cu–Ni(Au) and Sn–Au intermetallic compounds on the solder joint reliability of flip chips on low temperature co-fired ceramic substrates

The formation of intermetallic compounds in the solder joint of a flip chip or chip scale package depends on the under bump metallurgy (UBM), the substrate top surface metallisation, the solder alloy and the application conditions. To evaluate the influence of intermetallic compounds on the solder joint reliability, a detailed study on the influence of the UBM, the gold finish thickness of the substrate top surface metallisation, the solder alloy and the aging conditions has been conducted. Flip chips bumped with different solder alloys were reflow-mounted on low temperature co-fired ceramic substrates. The flip chip package was then aged at high temperature and a bump shear test followed to examine the shear strength of the solder joint at certain aging intervals. It was found that the type of UBM has a great impact on the solder joint reliability. With Ni(P)/Au as the UBM, well-documented gold embrittlement was observed when the gold concentration in the eutectic SnPb solder was about 3 wt%. When Al/Ni(V)/Cu was used as the UBM, the solder joint reliability was substantially improved. Copper dissolution from the UBM into the solder gives different intermetallic formations compared to Ni(P)/Au as UBM. The addition of a small amount of copper in the solder alloy changed the mechanical property of the intermetallic compound, which is attributed to the formation of Sn–Cu–Ni(Au) intermetallic compounds. This could be used in solving the problem of the AuSn₄ embrittlement. The formation and the influence of this Sn–Cu–Ni(Au) intermetallic phase are discussed. The gold concentration in the solder joint plays a role in the formation of intermetallic compounds and consequently the solder joint reliability, especially for the Sn–Ag–Cu soldered flip chip package.     

Thermo-mechanical reliability analysis of a RF SiP module based on LTCC substrate

The RF SiP module based on LTCC substrate has attracted considerable attention in wireless communications for the last two decades. However, the thermo-mechanical reliability of this 3D LTCC architecture has not been well-studied as common as its traditional ceramic package structure. A practical RF SiP module based on LTCC substrate was presented and its thermo-mechanical reliability was analyzed in this paper, with emphasis on the reliability of heat reflow process, the operating state and fatigue of second-level solder joints. The configuration and assembly process of the SiP module were briefly introduced at first, and qualitative analysis was made according to the reliability problem that may occur in the manufacturing process and the operating state. Through FEM simulation, this paper studied the warpage and stress variation of the RF SiP module, as well as parametric studies of some key package dimensions. Solder joint reliability under temperature cycling condition was also analyzed in particular in this paper. The results show that for the heat reflow process and operating state, the maximum warpage is both on the top LTCC substrate, but the maximum stresses are on the outermost solder ball and the kovar column at the corner, respectively. There is a large residual stress on the critical solder ball at the end of the reflow process and the key package dimensions has little effect on it. The thickness of top LTCC substrate has a significant impact on the thermal deformation and thermal stress, followed by the height of kovar columns. The reason for the considerable thermal stress on the kovar column is the non-uniform of temperature distribution. The key to reducing thermal deformation and stress in the operating state is the employment of effective cooling measures. It is found by comparison that the reliability of critical solder joints can be greatly improved by adding suitable underfill.