一种低压低功耗Rail-to-Rail运算放大器的设计

基于TSMC 0.18μm互补型金属氧化物半导体(CMOS)工艺,设计了一种2 V低功耗恒定跨导Rail-to-Rail运算放大器。该运算放大器的输入级采用并行N沟道和P沟道差分输入级,实现了Rail-to-Rail的共模输入范围;为使输入跨导在整个共模输入范围内基本恒定,采用三倍电流镜技术;输出级采用带有Cascode米勒补偿的AB类输出控制电路。在Cadence Spectre环境下仿真后的结果显示:直流增益为91 dB,相位裕度为84.5°,单位增益带宽为9.4MHz,功耗为0.2 mW,适合应用在各种低压低功耗场合。     

恒跨导轨对轨带有连续时间共模反馈的FDA设计

提出了一种恒跨导输入输出轨对轨带有连续时间共模反馈的全差分运算放大器。输入级互补差分对采用交叉导通实现输入总跨导在整个共模输入范围内保持恒定；中间级采用折叠共源共栅结构实现高增益和满摆幅。同时设计了一种连续时间共模反馈电路搭配A类输出结构，使FDA能够在大摆幅和高阻抗的系统下工作。基于SMIC 0.18 μm工艺对设计的FDA进行仿真验证与版图绘制，该电路在电源电压3.3 V，负载电容5 pF时，直流增益92.2 dB，单位增益带宽5.55 MHz，输入输出轨到轨范围接近100%，输入级跨导变化率仅4.53%，建立时间分别为218和195.7 ns，其对应的压摆率分别为15和16.7 V/μs。     

基于AD603程控增益大功率宽带直流放大器的设计

采用低噪声增益可程控集成运算放大器AD603和高频三极管2N2219和2N2905等器件设计了宽带直流放大器,该放大器具有增益可程控、功率高、频带宽、带宽可选择等特点。输入级采用两级AD603级联,以提高增益控制范围;中间级采用分立元件制作了高输出功率放大器,输出级设计了两路通频带分别为0～5MHz以及0～10MHz的低通滤波器实现带宽的可预置,通过51单片机可以对放大器增益和带宽进行控制。此外对提高直流放大器的各种性能指标提出了多种具体措施,在自动化要求较高的系统中具有很好的实用性。     

基于OPA820宽带放大器的设计

设计了一种宽带放大器,采用高速运算放大器OPA820和低失真电流反馈运算放大器THS3091构成两级放大电路,在6 Hz～20 MHz的通频带中实现放大增益为43 dB,具有带内波动小,输出噪声低的特点.同时将单一的5 V电源通过TPS61087和MC34063A产生系统所需要的正负电源为放大器供电.放大器输出经过精密...     

全差分低电压、高驱动能力运算放大器的实现

该文提出了一种全差分低电压、高驱动能力运算放大器电路,通过分析具有不同有源负载结构的差分放大器,得到具有反折电流镜有源负载的差分输入级电路具有较宽的共模输入范围.高效率的甲乙类输出级能提供轨对轨输出摆幅和高输出电流,由于电路具有特定拓扑结构的输出级,因而运算放大器能够工作在低电源电压状态下.采用台积电(TSMC)2层多晶硅、4层金属(2P4M)3.3V,0.35μmCMOS工艺流片得到所设计的全差分低电压、高驱动能力运算放大器在3.3V电源电压工作条件下的功耗仅为625μW,电流输出幅度达到1.2mA.     

高性能四通道数字可编程序运算放大器HA－2400

ＨＡ－２４００是一种具有四个相同输入级，一个输出级，输入与输出通过数字可控模拟开关相连的高性能组合运算放大器。该运放具有高的输入阻抗，低的失调电流，高的转换速率，宽的增益带宽，加之灵活的数字可控输出的功能，使各种新型电路的应用变成了现实。     

一种新颖的CMOS电流控制型可变增益放大器

采用0.35μm CMOS技术实现了一种增益按指数规律变化的电流控制型可变增益放大器(VGA)。通过采用Pseudo-exponential函数逼近方法设计指数发生电路,在1.5 V电压下工作所消耗的功率不超过1 mW。仿真结果表明,在输入控制电流误差为0.5 db的范围内,该VGA的增益控制范围可以达到30 db,适用于各种模拟信号处理电路。     

高性能四通道数字可编程序运算放大器HA—2400

ＨＡ－２４００是一种具有四个相同输入级，一个输出级，输入与输出通过数字可控模拟开关相连的高性能组合运算放大器，该运放具有高的输入阻抗，低的失调电流，高的转换速率，宽的增益带宽，加之灵活的数字可控输出的功能，使各种新型电路的应用变成了现实。     

采用1.75 Gbps串行发送器的低功耗14位125 MSPS ADC

提供了一种适宜于多通道集成的低功耗、小面积14位125 MSPS流水线模数转换器(ADC)。该ADC基于开关电容流水线ADC结构,采用无前端采样保持放大器、4.5位第一级子级电路、电容逐级缩减和电流模串行输出技术设计并实现。各级流水线子级电路中所用运算放大器使用改进的"米勒"补偿技术,在不增加电流的条件下实现了更大带宽,进一步降低了静态功耗;采用1.75 Gbps串行数据发送器,数据输出接口减少到2个。该ADC电路采用0.18μm 1P5M 1.8 V CMOS工艺实现,测试结果表明,该ADC电路在全速采样条件下对于10.1 MHz的输入信号得到的SNR为72.5 d BFS,SFDR为83.1 d B,功耗为241 m W,面积为1.3 mm×4 mm。     

适用于DCS1800/PCS1900的手持设备射频前端低噪声放大器设计

根据DCS1800和PCS1900的系统指标要求,采用全差分源级退化电感和共源共栅结构设计了一款适用于DCS1800/PCS1900双频手持设备的低噪声放大器电路并实现了高增益、低增益和旁路三种工作模式。电路采用TSMC 0.18μm CMOS工艺设计,仿真结果表明：在双频模式下,该低噪声放大器电路的最大电压增益分别是20.3dB和20.9dB,最小噪声系数分别是1.6dB和1.63dB,在1.8V电源电压下电流为5.5mA。     

Rail-to-rail input/output operational transconductance amplifier (OTA) with high CMRR and PSRR

This paper introduces a low-voltage CMOS operational transconductance amplifier (OTA) with rail-to-rail input/output stages. Input stage uses floating gate transistors to realize rail-to-rail scheme. However, this scheme gives rise to reduction in transconductance of the OTA. To increase transconductance (G _m), an effective partial positive feedback is used. Class AB output stage is so designed that improves the gain, slew rate, common mode rejection ratio and maximum swing of the OTA. With ±0.75 v power supply, this OTA consumes the low power of 397.5?μw. G _m variation of input stage is 0.004% for rail-to-rail (±0.75 v) variation in common mode input signals and reaches to 0.036% beyond the rail-to-rail range (±1 v) which is a superior result compared with previously reported works. As is proved by theoretical relations and simulation results, proposed auxiliary circuit for rail-to-rail operation results in both high CMRR due to fixing common source node of input differential pair and high linearity due to attenuation of input signals. Simulation results show that CMRR in DC frequency is 259.5 dB and HD3 is ?46 dB for 2.15 v_P-P differential output voltage signal with applying a 0.48 v_P-P input signal at 1 MHz. Proposed OTA is simulated in TSMC 0.18 μm CMOS technology with Hspice. Monte Carlo simulation results are included to forecast mismatch effects after fabrication process.     

Class AB amplifier with enhanced slew rate and GBW

The design of a micropower class AB operational transconductance amplifier with large dynamic current to quiescent current ratio is addressed. It is based on a compact and power-efficient adaptive biasing circuit and a class AB current follower using the quasi-floating gate (QFG) technique. The amplifier has been designed and fabricated in a 0.5-μm CMOS process. Simulation and measurement results show a slew rate (SR) improvement factor versus the class A version larger than 4 for the same supply voltage and bias currents, as well as enhanced small-signal performance.     

Enhanced active‐feedback frequency compensation with on‐chip‐capacitor reduction feature for amplifiers with large capacitive load

A large capacitive load amplifier with enhanced active‐feedback frequency compensation is proposed in this paper. The enhancement is achieved through using a wide‐bandwidth scalar circuit to increase the transconductance of the output stage so that the overall bandwidth of the amplifier can be extended considerably. Implemented in a standard CMOS 130‐nm technology, with a supply of 0.7 V and consuming 27 μA of current, the amplifier drives a load capacitor of 15 nF. No on‐chip resistor is needed; only a 0.91‐pF compensation capacitor is used to maintain stability. The achieved gain‐bandwidth product and phase margin are 1.28 MHz and 66.9°, respectively. Moreover, the slew rate is 0.263 V/μs. The active chip area is 0.0056 mm². Copyright © 2017 John Wiley & Sons, Ltd.     

A novel circuit element and its application in signal amplification

A novel IC‐based current amplifier configuration for signal‐processing applications that can be configured using commercially available integrated circuit elements is presented. The circuit is accurate, has a wide bandwidth and can drive grounded loads. It utilizes a CCII+ type current conveyor with its input circuit in the feedback loop of a current feedback amplifier (CFA). In the current amplifying mode, the circuit has a low input impedance over a broad frequency range which never rises above the low input impedance of the inverting input of the associated CFA. Experimental results obtained using AD844s confirm the results derived. Copyright © 2007 John Wiley & Sons, Ltd.     

Low‐voltage bulk‐driven input stage with improved transconductance

A low‐voltage input stage constructed from bulk‐driven PMOS transistors is proposed in this paper. It is based on a partial positive feedback and offers significant improvement of both input transconductance and noise performance compared with those achieved by the corresponding already published bulk‐driven structures. The proposed input stage offers also extended input common‐mode range under low supply voltage in relevant to a gate‐driven differential pair. A differential amplifier based on the proposed input stage is also designed, which includes an auxiliary amplifier for the output common‐mode voltage stabilization and a latch‐up protection circuitry. Both input stage and amplifier circuits were implemented with 1 V supply voltage using standard 0.35µm CMOS process, and their performance evaluation gave very promising results. Copyright © 2010 John Wiley & Sons, Ltd.     

一种时间测量单元（TMU）的仿真及研究

文中重点探讨了ＩＣ交流时间参数的一种测量方法的基本原理，例如测试运算放大器的压摆率及比较器的时间延迟参数。推导了这种测量电路的数学模型，。用计算机进行了仿真并对仿真的结果进行了分析。     

Study and implementation of a 15‐W driver for piezoelectric actuators

This paper studies and implements a 15‐W driver for piezoelectric actuators. The discussed driver is mainly composed of a flyback converter and a power operational amplifier (P‐OPA). The flyback converter produces a variable DC voltage to supply the P‐OPA, which outputs an amplified sinusoidal signal with a DC bias of 100 V to drive the piezoelectric actuator. The power losses can be reduced because the supply voltage of the P‐OPA varies with the peak of the input signal. The power conversion efficiency of the driver can thus be promoted up to more than 30%. From the experimental results, the implemented prototype possesses some advantageous features, such as a nearly constant output‐to‐input voltage gain, a high slew rate, a high input impedance, a low output impedance, and low output voltage ripples. Copyright © 2016 John Wiley & Sons, Ltd.     

Super class AB OTA without open‐loop gain degradation based on dynamic cascode biasing

A scheme to achieve simultaneously extremely high slew‐rate improvement and avoiding open‐loop gain degradation in one‐stage super class AB op‐amps is introduced. It overcomes the serious shortcoming of super class AB operational transconductance amplifiers that shows very high‐output current enhancement factors at the expense of degrading the open‐loop gain. The proposed scheme uses dynamically biased cascode transistors to avoid gain and slew‐rate degradation. Experimental results of a super class AB operational transconductance amplifier in 180‐nm complementary metal‐oxide semiconductor technology with open‐loop gain of 67 dB, a factor 2 improvement in GBW , and a current enhancement factor of 270 verify the proposed scheme. Copyright © 2017 John Wiley & Sons, Ltd.     

A 300‐mA load CMOS low‐dropout regulator without an external capacitor for SoC and embedded applications

This study proposes a 300‐mA external capacitor‐free low‐dropout (LDO) regulator for system‐on‐chip and embedded applications. To achieve a full‐load range from 0 to 300 mA, a two‐scheme (a light‐load case and a heavy‐load case) operation LDO regulator with a novel control circuit is proposed. In the light‐load case (0–0.5 mA), only one P‐type metal–oxide–semiconductor input‐pair amplifier with a 10‐pF on‐chip capacitor is used to obtain a load current as low as 0. In the heavy‐load case (0.5 to 300 mA), both P‐type metal–oxide–semiconductor and N‐type metal–oxide–semiconductor differential input‐pair amplifiers with an assistant push‐pull stage are utilized to improve the stability of the LDO regulator and achieve a high slew rate and fast‐transient response. Measurements show an output voltage of 3.3 V and a full output load range from 0 to 300 mA. A line regulation of 1.66 mV/V and a load regulation of 0.0334 mV/mA are achieved. The measured power‐supply rejection ratio at 1 kHz is −65 dB, and the measured output noise is only 34 μV. The total active chip size is approximately 0.4 mm² with a standard 0.5 μm complementary metal–oxide–semiconductor process. Copyright © 2017 John Wiley & Sons, Ltd.     

A nonlinear macromodel for operational amplifiers

A general-purpose nonlinear macromodel of an operational amplifier is presented. All element values can be derived directly from typical specification sheets eliminating any testing to determine model parameters. The model simulates the following characteristics: voltage and current offsets, input impedance, nonlinear input bias currents, gain, multiple poles, nonlinear slew, common-mode gain, voltage and current limiting and output impedance.