一种SiC MOSFET串扰抑制的谐振辅助驱动电路

随着SiC MOSFET开关频率的不断增加,逆变器桥臂串扰现象越发严重并易造成桥臂直通短路,这限制了SiC MOSFET开关频率的进一步提高。该文提出一种SiC MOSFET串扰抑制的谐振辅助驱动电路,通过在栅源之间添加电容电感辅助谐振电路,能够在SiC MOSFET关断期间完成负压到零压的变化,同时不需要使用有源器件。当SiC MOSFET开通时,辅助电路让栅极电压从0.7V上升而非负压上升,相较于传统驱动电路,开关速度更快、开关损耗更低;而且同时具备抑制正向串扰和反向串扰的优点。该文分析电路的参数设置,并通过仿真和实验验证了该电路相对于传统驱动电路的优势。     

一种抑制SiC MOSFET桥臂串扰的改进门极驱动设计

由于传统驱动下碳化硅(SiC)MOSFET受高开关速度特性及寄生参数影响,桥臂串扰现象更加严重,而现有抑制串扰驱动电路又往往会增加开关损耗、开关延时和控制复杂程度,因此本文结合驱动阻抗控制与负压关断的串扰抑制方法,提出一种改进门极驱动电路。首先,阐述串扰现象产生原理及其典型抑制方法。其次,在负压关断前提下,基于控制辅助三极管开断,降低串扰产生过程中驱动回路阻抗的思想,提出一种在栅源极增加三极管串联电容新型辅助支路的改进驱动方法,并分析其工作原理,研究改进驱动电路关键参数设计原则。最后,搭建双脉冲测试实验平台,在不同驱动电阻、输入电压、负载电流条件下对改进驱动电路设计的有效性进行验证。结果表明,传统驱动下SiC MOSFET桥臂串扰现象明显。相比典型抑制串扰驱动电路,提出的驱动方法在有效抑制串扰同时,减小了开关损耗与开关延时。     

抑制SiC MOSFET桥臂串扰与栅源电压振荡的推挽式电容辅助电路分析及参数设计方法

碳化硅金属–氧化物半导体场效应晶体管(SiC metal-oxide-semiconductor field-effect transistor, SiC MOSFET)在高速开关中引起的桥臂串扰和栅极电压振荡严重制约了其开关速度。针对已提出的基于推挽式电容辅助电路(push-pull-capacitor auxiliary circuit, PPCAC)的SiC MOSFET驱动工作过程进行了进一步的分析。结合分析，将SiC MOSFET桥臂串扰以及漏源电压振荡引起的栅源电压振荡2个问题归一化，通过推挽电容充放电时刻以及桥臂串扰约束，提出了一种推挽电容参数设计方法。通过该设计方法，可使得PPCAC在抑制SiC MOSFET桥臂串扰与栅源电压振荡的基础上，改善其开通关断速度。实验结果验证了所提出设计的有效性。     

一种提高SiC MOSFET在高开关速率下栅极电压稳定性的驱动电路

高开关速率且栅极电压稳定的驱动是SiC MOSFET高频工作、进而实现功率变换系统小型化和轻量化的关键技术之一。针对如何在高开关速率下稳定驱动SiC MOSFET,并实现可靠的短路保护,根据栅源电压干扰的传导特点,基于辅助器件的跨导增益构建负反馈控制回路,提出一种SiC MOSFET栅极驱动,进而研究揭示该驱动的短路保护策略。首先,基于跨导增益负反馈构造栅极驱动电路并分析其工作原理;其次,研究该驱动的串扰抑制能力与短路保护特性;最后,通过实验证明基于跨导增益负反馈的栅极驱动电路的可行性,及其在串扰抑制和短路保护中的有效性。     

半桥结构中的SiC MOSFET串扰电压建模研究

SiC MOSFET凭借着低开关损耗、高工作频率与高工作温度点等优点,逐渐在高效率、高功率密度与高温的应用场合取代传统的硅功率器件。然而,在高速开关中带来的栅极串扰现象严重制约SiC器件的开关速度。传统的串扰抑制方法重点关注由栅极–漏极寄生电容引入的干扰电压,往往通过减小驱动回路阻抗的方式来降低串扰电压。该文基于SiC MOSFET器件的开关模态,提出考虑共源电感的分段线性化串扰电压模型。该模型基于器件数据手册及双脉冲实验提取的参数,考虑栅极–漏极电容、共源电感、体二极管反向恢复等非理想因素的影响。对比不同电压点、电流点与电阻值下实验与模型的输出结果。该模型表明,串扰电压是由器件栅极–漏极电容、共源电感与驱动回路阻抗共同作用的结果。单一降低驱动回路阻抗的方式对串扰电压的抑制效果有限。基于提出的模型,该文给出串扰电压抑制的指导方法,可直接用于SiC MOSFET驱动电路的设计。     

一种改进型抑制SiC MOSFET桥臂串扰的门极驱动设计

由于传统驱动中SiC MOSFET在高开关频率的情况下其寄生参数造成的桥臂串扰更加严重,而现有的抑制串扰驱动电路大多是以增加开关损耗,增长开关延时和增加控制复杂度为代价抑制串扰。因此,根据降低串扰产生过程中驱动回路阻抗的思想,提出一种在栅源极间增加PNP三极管串联二极管和电容的新型有源密勒钳位门极驱动设计,并分析其工作原理,对改进驱动电路并联电容参数进行计算设计。最后,搭建了直流母线电压为300V的同步Buck变换器双脉冲测试实验平台,分别与传统串扰抑制电路,典型串扰抑制电路的正负向串扰电压尖峰抑制效果和开通关断速度做对比分析。实验结果表明,提出的串扰抑制驱动电路正负向电压尖峰分别比传统和典型串扰抑制电路降低了80%和40%,同时减少了32%的器件开关延时。     

一种新型SiC MOSFET驱动电路的设计

与传统硅基器件相比,碳化硅(SiC)器件的开关速度得到大幅改善,提高了变换器的功率密度与效率。然而过大的开关频率引起更为严重的栅极串扰问题,造成器件失效。分析了SiC金属-氧化物-半导体场效应晶体管(MOSFET)的开关过程与串扰产生原理,详述其设计过程,分析了外并电容的抑制串扰驱动电路,最后设计出一种带有信号隔离功能的可抑制栅极串扰的负压驱动电路。实验结果表明,所设计的SiC MOSFET驱动电路的驱动波形高低电平分明,而且有效抑制了栅极串扰问题,大幅减小器件的开关延时时间,降低了开关损耗。     

SiC MOSFET开关特性及多等级栅电压驱动电路

针对新型宽禁带功率半导体器件碳化硅(SiC)金属-氧化物半导体场效应晶体管(MOSFET),为了充分发挥其在高功率密度和高效率应用场合中的高速及低功耗特性,分析了SiC MOSFET的开关特性,提出了一种基于复杂可编程逻辑器件(CPLD)的新型多等级栅电压驱动电路(MGD)。在SiC MOSFET开关不同阶段,通过调整栅极驱动电压以改善其开关特性。与传统驱动电路(CGD)相比,提出的MGD在相同门极驱动电阻与栅源极电容前提下,能有效提高开关速度,降低电压电流尖峰、降低开关损耗。最后通过双脉冲实验,分析了栅极驱动电阻,栅源极电容对开关特性的影响,验证了MGD在改善开关特性方面具有明显的优越性。     

碳化硅MOSFET桥臂串扰机理分析与抑制策略EI北大核心CSCD

桥臂串扰指关断态开关管驱动端状态受到同一桥臂支路另一开关管开通或关断的干扰而产生扰动。相比于传统硅器件,碳化硅金属–氧化物半导体场效应晶体管(metal-oxide-semiconductor field effect transistor,MOSFET)开关速度更高、驱动端可靠关断区间更小,因此,其桥臂串扰问题更加突出。为提高碳化硅MOSFET可靠性,有必要分析碳化硅MOSFET桥臂串扰发生过程和特点,并提出相应解决方案。为此,文中首先建立基于碳化硅MOSFET桥臂串扰电路模型,并分析该模型暂态过程;其次,基于分析结果建立桥臂串扰电压极值简化模型,并提出基于桥臂串扰问题安全工作区模型,然后,由此提出并设计具有桥臂串扰抑制功能的栅极驱动电路;最后,通过实验验证所提桥臂串扰模型的可行性,以及所提栅极驱动电路的有效性。     

多管并联SiC MOSFET驱动电路串扰抑制方法

为解决大功率高频串联谐振逆变器中多管并联碳化硅(SiC)金属-氧化物半导体场效应晶体管(MOSFET)驱动电路存在的串扰问题,分析了驱动电路串扰问题产生的机理和常用驱动串扰抑制方法,优化了驱动电路结构和器件参数,设计了一种具有串扰抑制作用的多管并联SiC MOSFET驱动电路。搭建了一台SiC MOSFET高频H桥串联谐振逆变电源样机,对驱动电路进行了相关测试,验证了所设计的驱动电路可有效抑制串扰。     

On-the use of IGBT-gated GTO-cascode switches in quasi-resonantconverters

The gate turn-off (GTO) thyristor has the highest voltage and current rating among the semiconductor power switches used extensively today. This paper documents the use of an insulated gate bipolar transistor (IGBT) to improve switching performance of a GTO in a cascode switch. The IGBT-gated GTO-cascode switch features simple drive requirement, fast switching, robustness, and overcurrent protection. The cascode switch was applied in a quasi-resonant buck converter and simulated on a computer using PSPICE. Results indicate that IGBT-gated GTO-cascode switches are promising candidates for high-power and high-frequency applications     

Characteristics and utilization of a new class of low on-resistanceMOS-gated power device

A new class of MOS-gated power semiconductor devices Cool MOS (Cool MOS is a trademark of Infineon Technologies, Germany) has been introduced with a supreme conducting characteristic that overcomes the high on-state resistance limitations of high-voltage power MOSFETs. From the application point of view, a very frequently asked question immediately arises: does this device behave like a MOSFET or an insulated gate bipolar transistor (IGBT)? The goal of this paper is to compare and contrast the major similarities and differences between this device and the traditional MOSFET and IGBT. In this paper, the new device is fully characterized for its: (1) conduction characteristics; (2) switching voltage, current, and energy characteristics; (3) gate drive resistance effects; (4) output capacitance; and (5) reverse-bias safe operating areas. Experimental results indicate that the conduction characteristics of the new device are similar to the MOSFET but with much smaller on-resistance for the same chip and package size. The switching characteristics of the Cool MOS are also similar to the MOSFET in that they have fast switching speeds and do not have a current tail at turn-off. However, the effect of the gate drive resistance on the turn-off voltage rate of rise (dv/dt) is more like an IGBT. In other words, a very large gate drive resistance is required to have a significant change on dv/dt, resulting in a large turn-off delay. Overall, the device was found to behave more like a power MOSFET than like an IGBT     

寄生电感对于功率MOSFET开关特性的影响

分散在MOSFET栅极、源极、漏极的寄生电感由于封装以及印制电路板（PCB）走线,改变了MOSFET的开关特性。通过仿真分析对比,指出MOSFET寄生电感存在如下特性：源极电感对栅极驱动形成负反馈,导致开关速度变慢,采用开尔文连接,可以将栅极回路与功率回路解耦,提高驱动速度;在米勒效应发生时刻需要合理地降低栅极电感来降低栅极驱动电流;漏极电感通过米勒电容影响MOSFET的开通速度,在关断时刻导致电压应力增加;在并联的回路当中,非对称的布局将导致MOSFET之间的动态不均流;当MOSFET在开关过程中,环路电感与MOSFET自身的结电容产生振荡时,可以在电路增加吸收电容减小环路电感,改变振荡特性。     

Improved zero-current transition converters for high-powerapplications

Existing zero-current transition (ZCT) converters do not solve main switch turn-on problems and require auxiliary switches to be turned off with high current and, therefore, are not suitable for high-power applications. Novel ZCT schemes proposed in this paper enable all main switches and auxiliary switches to be turned on and off under zero-current conditions. The zero-current switching at both turn-on and turn-off not only reduces switching losses significantly, but also eliminates the need for passive snubbers, due to the much reduced switch stress. The cost of the auxiliary switches can he reduced compared to the existing ZCT schemes, due to their zero-current turnoff. The proposed technology is well suited for DC-DC and three-phase converters with insulated gate bipolar transistors (IGBTs), MOS-controlled thyristors (MCTs), and gate-turnoff switches (GTOs). Theoretical analysis, computer simulation, and experimental results are presented to explain the proposed schemes     

集成门极换向晶闸管开关特性

新型开关器件集成门极换向晶闸管(IGCT)由于其优越的性能在中高压大功率多电平变流器系统中逐渐得到广泛应用.在电力电子仿真软件PSIM中实现的一种适用于高压大功率变流仿真的IGCT功能模型的基础上,建立了IGCT单管实验的仿真模型,分析了IGCT开关特性,特别是该电路中各种杂散参数和缓冲吸收电路中各元件参数对IGCT关断过程的影响,为实际的基于IGCT器件的大功率多电平变流器系统的结构设计和控制提供了重要的理论根据和指导.     

Assignment of turn-on and turn-off power and energy losses in a GTO

The authors discuss the turn-on and turn-off losses in a gate turn-off (GTO) thyristor which must be properly accounted for because they can comprise upwards of 60% of the total losses. The authors attempt to discuss and clarify the definitions of power loss and energy per pulse for the turn-on and turn-off intervals. It is shown that prior work defining turn-on and turn-off power and energy losses does not adequately include all losses associated with the turn-on and turn-off events. Thus, it will be difficult to account for all those losses determining the heating effects of the GTO unless improvements are made. An example shows that the error can be substantial (8 to 15%). For this reason, improved definitions that have an underestimation of only 1 to 2% of the switching losses have been proposed. It was also found that the gate losses during the turn-off event must be accounted for and that improved measuring techniques and instrumentation are both necessary and possible     

Analysis and implementation of a new zero current switching flyback inverter

In this paper, a novel zero current switching (ZCS) flyback inverter in discontinuous conduction mode (DCM) is proposed. In the proposed flyback inverter, the ZCS for the primary switch is achieved by adding a simple auxiliary circuit to the conventional flyback inverter. Also, the auxiliary switch is turned on and turned off at ZCS condition. Therefore, the switching losses of the switches are negligible, which increases the efficiency and allows higher switching frequency and more compact design. The resonant auxiliary cell is activated only in short transition times that makes its conduction losses negligible. Furthermore, the voltage overshoot of the main switch is limited during the turn-off process, which allows utilization of lower voltage metal-oxide semiconductor field-effect transistors (MOSFETs) with low conduction losses and low cost. The detailed operation of the flyback inverter with auxiliary circuit and design considerations are presented. Simulation and experimental results are presented to verify the performance of the proposed inverter.     

Double-stage gate drive circuit for parallel connected IGBT modules

Solid state modulators are increasingly being used in pulsed power applications. In these applications IGBT modules must often be connected in parallel due to their limited power capacity. In a previous paper, we introduced a control method for balancing the currents in the IGBTs. In this paper, we investigate techniques to minimize the modules' rise and fall times, which can positively impact the modulator's output pulse parameters, which in turn must meet the application's specifications. Further, a reduction in rise and fall times lowers switching losses and thus increases the modulator's efficiency. To reduce the voltage rise time of the pulse without increasing the maximal over-voltage of the parallel IGBTs we have investigated a double-stage gate driver with protection circuits to avoid over-voltages and over-currents. Additionally voltage edge detection has been implemented to improve current balancing. Our measurement results reveal the dependency of the rise-time and turnoff losses on the design parameters of the gate drive. We show that our design achieves a 62% reduction in the turn-off rise time, and a 32% reduction in the turn-off losses.     

Fast switch fault diagnosis for PWM DC–DC low power converters

In this paper, a fast switching fault diagnostic scheme is proposed for low‐power pulse width modulation (PWM) DC–DC converters operating in different conduction modes. The outstanding feature of the proposed scheme is that no additional sensing circuits are needed. This is achieved by using the differential of output ripple voltage and the switch gate driver signal for diagnosis. Since the output voltage has to be normally measured for control purposes and the PWM signals are known to the controller, no additional sensors are needed in the proposed scheme. Moreover, based on the real‐time output voltage measurement and switch gate driver signal, the characteristics of switch open‐ and short‐circuit faults can be rapidly extracted, specifically, in less than one switching cycle. Besides, the fault detection scheme can be implemented by a low‐cost logical hardware circuit, which can be integrated into the control unit. The fault diagnosis principle, design considerations, and implementation of the detection scheme are discussed in this paper. Experimental results show that the fault detection system can detect the switching fault in four‐tenths of the switching period. Besides, the proposed method can be used in the applications where the output voltage ripple rate is more than 4%, which covers most situations. © 2017 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.