基准集在嵌入式系统性能分析中的应用

为准确评估嵌入式系统性能,量化分析嵌入式系统中关键部件对嵌入式系统整体性能的影响,充分发挥嵌入式处理器的性能,提出基于CoreMark基准集的嵌入式系统性能分析方法。基于开源的Leon2处理器,搭建一套用于工业控制的嵌入式系统;分析CoreMark基准集的特点和结构,将CoreMark基准集移植到嵌入式系统中;分析嵌入式系统可配置的关键部件,运用对比策略进行性能测试,得到嵌入式系统中关键部件的性能加速比,对嵌入式系统进行宏观和微观的性能分析。     

流水—减水MPP系统广播延迟的有效方法*

大规模并行处理系统中的通讯开销是影响系统性能的一个重要因素．广播操作是MPP系统中常用的通讯方式，快速地实现广播将有助于提高系统的性能．本文基于TORUS互连网络，提出了实现广播的流水方式,并分析丁它的性能，指出采用流水方式进行广播，可以减少广播延迟，改进系统的性能．     

动态部分重配置及其FPGA实现

动态部分重配置充分利用了FPGA芯片提供的可重配置功能，提高了FPGA芯片的利用率，减小了FPGA芯片的配置时间，有效地提高了系统的整体性能。该文介绍了动态部分重配置的两种实现方法，并在Spartan-II FPGA上进行了验证。     

网络通信流Multi-agent用于应用系统性能评价研究

核心业务系统整体性能不佳可能导致系统在大业务量时出现功能、效率和安全性问题,因此系统的整体性能成为业界关注重点.现代的信息系统中新型软件架构层出不穷,软硬件和网络通讯之间的相互关联作用日益复杂,加大了系统性能瓶颈查找的难度.本文研究如何通过多智能代理技术等方法,截取、分析和回放网络数据流来测量软件性能.智能代理使得整个测试的各个分支具有通讯、协作的能力.依此模型方法,在两个大型业务系统进行了性能评价实测验证,证明此方法具有一定的优越性.     

通讯技术在电动汽车充电站中的应用设计

针对智能充电站的应用要求,提出通讯技术在电动汽车充电站中的设计方案。论述充电站的监控系统三层通讯整体结构;提出充电机监控系统双CAN通讯网络;对充电站主要设备充电机、充电桩的内部多种通讯方式和功能进行描述和方案设计;对通讯过程中采用的CAN通讯、以太网和串行通讯接口进行设计并对其通讯协议进行讨论和说明。     

以知识点为特征的网上学习系统设计模式探讨

该文探讨了以知识点为特征的网上学习系统的设计思想和设计模式,从整体上对其功能模块进行了分析,讨论了系统设计的性能优化方法,并给出了系统的人员管理与通讯以及安全性管理的方法,     

流水—减少MPP系统广播延迟的有效方法

大规模并行处理系统中的通讯开销是影响系统性能的一个重要因素，广播操作是ＭＰＰ系统中常用的通讯方式，快速地实现广播将有助于提高系统的性能，本文基于ＴＯＲＵＳ互连网络，提出了实现广播的流水方式，分析了它的性能，指出采用流水方式进行广播，可以减少广播延迟，改进系统的性能。     

横河CS3000系统中的Profibus通讯技术的应用

文章主要利用横河公司所开发的CS3000系统结合西门子公司所研发的S7-300系统来介绍Profibus通讯技术的应用，其分别从其硬件配置、软件配置以及网络组态等方面进行了详细阐述，提出了其网络组态的步骤及其实现通讯的具体方法，说明了利用Profibus通讯技术可有效提高企业生产力及经济效益。     

基于TD-SCDMA系统的抗干扰联合检测研究

随着3G通讯系统迅猛发展,特别是在TD-SCDMA系统中存在着各种干扰问题,影响和制约了系统本身容量和性能的提高。以多径干扰为例,首先通过理论和实验分析,提出一种新的抗干扰联合检测技术来消除多径干扰,然后在现有的硬件设备和系统软件配置基础上,通过比较分析两种自适应算法,选择采用合适的算法来完成TD-SCDMA系统的优化和升级,有助于提高系统容量和信道正交质量。     

微机电网监测通讯系统

介绍两级微机进行电网监测的通讯管理系统，说明了系统的硬件配置、系统功能及软件设计。     

Dynamic reconfiguration of node location in wormhole networks

Several techniques have been developed to increase the performance of parallel computers. Reconfigurable networks can be used as an alternative to increase the performance. Network reconfiguration can be carried out in different ways. Our research has focused on distributed memory systems with dynamic reconfiguration of node location. Briefly, this technique consists of positioning the processors in the network depending on the existing communication pattern among them, to suit the requirements of each computation.In this article, we present a dynamic reconfiguration technique for wormhole networks. We have used both a crossbar and a multistage interconnection network to implement a reconfigurable logical two-dimensional (2-D) torus topology. The reconfiguration mechanism is based on a distributed reconfiguration algorithm. The algorithm is based on a cost function that requires only local information. We discuss reconfiguration features and adjust the different parameters of the reconfiguration algorithm. We have also studied the deadlock problem in reconfigurable wormhole networks, and give details of our solution. Finally, we have evaluated the performance of this technique under several workloads.     

Self-organization of reconfigurable protocol stack for networked control systems

In networked control systems (NCS), the control performance depends on not only the control algorithm but also the communication protocol stack. The performance degradation introduced by the heterogeneous and dynamic communication environment has intensified the need for the reconfigurable protocol stack. In this paper, a novel architecture for the reconfigurable protocol stack is proposed, which is a unified specification of the protocol components and service interfaces supporting both static and dynamic reconfiguration for existing industrial communication standards. Within the architecture, a triple-level self-organization structure is designed to manage the dynamic reconfiguration procedure based on information exchanges inside and outside the protocol stack. Especially, the protocol stack can be self-adaptive to various environment and system requirements through the reconfiguration of working mode, routing and scheduling table. Finally, the study on the protocol of dynamic address management is conducted for the system of controller area network (CAN). The results show the efficiency of our self-organizing architecture for the implementation of a reconfigurable protocol stack.     

可重构密码处理结构中重构机制及对性能的影响

重构机制对可重构密码处理系统的性能有着重要的影响,该文从全局、局部、静态、动态几方面提出了流水化可重构密码处理结构中重构机制的分类,给出了各种机制的吞吐率和延迟公式,并分析了几种机制的性能和实现代价,最后给出了在采用局部动态重构机制的可重构密码处理结构中密码处理的性能。     

基于Jennic平台的WSN语音通信系统

通过对无线传感器网络语音通信方面的研究,提出一种以无线传感器JN5139节点和音频解码器WM8510为硬件基础的无线传感器网络语音通信方案,论述传感器网络建立语音通信的基本流程及软件实现方法,给出无线传感器网络语音通信性能的评估体系,基于实用性的标准对评估结果进行简要分析。     

通信延迟条件下无人机编队重构的自主安全控制

多架无人机协同执行任务是未来网络化战场上的一种重要作战要求,然而复杂战场环境的变化极大地影响无人机编队的生存能力.为了自主安全地实现复杂战场环境中存在通信延迟的无人机编队重构控制,构建基于分层结构的无人机编队重构的自主安全控制架构.然后,提出一种基于纳什谈判的分布式预测控制(Nash bargaining solution-distributed model prediction control,NBS-DMPC)的新方法.针对存在通信延迟的问题,设计了基于信息滤波算法的信息补偿方法.最后,仿真实验表明所提算法能够自主安全地控制无人机编队重构并能有效降低问题的求解规模.同时仿真结果也验证了所提信息滤波算法在通信时延下的有效性.     

Dynamic objects: Supporting fast and easy run-time reconfiguration in FPGAs

Partial reconfiguration capabilities must be exploited to obtain the maximum benefits from dynamically reconfigurable FPGAs. Partial reconfiguration process management still faces a set of open problems that have thus far made it impossible to take full advantage of partial and dynamic reconfiguration. The work presented in this article proposes a novel architecture, development workflow, and modelling approach for dynamically reconfigurable systems management using an object model that offers a global solution. This solution is built on a system-level middleware that provides the infrastructure and tools for communication between different components in heterogeneous embedded systems. Several experiments were performed to test and evaluate each part of our proposed solution, and the obtained results are presented. These results demonstrate the excellent performance of our proposed solution.     

A multi-application approach for synthesizing custom network-on-chips

Execution of multiple applications on Multi-Processor System-on-Chips (MPSoCs) significantly boosts performance and energy efficiency. Although various researchers have suggested Network-on-Chip (NoC) architectures for MPSoCs, the problem still needs more investigations for the case of multi-application MPSoCs. In this paper, we propose a fully automated synthesis flow in five steps for the design of custom NoC fabrics for multi-application MPSoCs. The steps include: preprocessing, core to router allocation, voltage island merging, floorplanning, and router to router connection. The proposed flow finds design solutions that satisfy the performance, bandwidth, and power constraints of all input applications. If the user decides, the proposed synthesis adds network-level reconfiguration to improve the efficiency of the obtained design solutions. With the reconfiguration option, the proposed flow comes up with adaptive NoC architectures that satisfy each application’s communication requirements while power-gate idle resources, e.g., router ports and links. If reconfiguration option is not set by the user, the proposed flow considers the top communication requirements among the applications in finding design solutions. We have used the proposed synthesis flow to design custom NoCs for several combined graphs of real-world applications and synthetic graphs. Results show that the reconfiguration option can save up to 98% in the energy-delay product (EDP) of the ultimate designs.

     

Evaluating the impacts of dynamic reconfiguration on the QoS of running systems

A major challenge in dynamic reconfiguration of a running system is to understand in advance the impact on the system's Quality of Service (QoS). For some systems, any unexpected change to QoS is unacceptable. In others, the possibility of dissatisfaction increases due to the impaired performance of the running system or unpredictable errors in the resulting system. In general it is difficult to choose a reasonable reconfiguration approach to satisfy a particular domain application. Our investigation on this issue for dynamic approaches is four-fold. First, we define a set of QoS characteristics to identify the evaluation criteria. Second, we design a set of abstract reconfiguration strategies bringing existing and new approaches into a unified evaluation context. Third, we design a reconfiguration benchmark to expose a rich set of QoS problems. Finally, we test the reconfiguration strategies against the benchmark and evaluate the test results. The analysis of acquired results helps to understand dynamic reconfiguration approaches in terms of their impact on the QoS of running systems and possible enhancements for newer QoS capability.     

A coarse-grain reconfigurable architecture for multimedia applications supporting subword and floating-point calculations

Signal processors exploiting ASIC acceleration suffer from sky-rocketing manufacturing costs and long design cycles. FPGA-based systems provide a programmable alternative for exploiting computation parallelism, but the flexibility they provide is not as high as in processor-oriented architectures: HDL or C-to-HDL flows still require specific expertise and a hardware knowledge background. On the other hand, the large size of the configuration bitstream and the inherent complexity of FPGA devices make their dynamic reconfiguration not a very viable approach. Coarse-grained reconfigurable architectures (CGRAs) are an appealing solution but they pose implementation problems and tend to be application specific. This paper presents a scalable CGRA which eases the implementation of algorithms on field programmable gate array (FPGA) platforms. This design option is based on two levels of programmability: it takes advantage of performance and reliability provided by state-of-the-art FPGA technology, and at the same time it provides the user with flexibility, performance and ease of reconfiguration typical of standard CGRAs. The basic cell template provides advanced features such as sub-word SIMD integer and floating-point computation capabilities, as well as saturating arithmetic. Multiple reconfiguration contexts and partial run-time reconfiguration capabilities are provided, tackling this way the problem of high reconfiguration overhead typical of FPGAs. Selected instances of the proposed architecture have been implemented on an Altera Stratix II EP2S180 FPGA. On this system, we mapped some common DSP, image processing, 3D graphics and audio compression algorithms in order to validate our approach and to demonstrate its effectiveness by benchmarking the benefits achieved.     

内容发布订阅系统的订阅重构算法研究

在内容发布/订阅系统中,针对传统订阅重构算法存在订阅冲突等问题,提出一种适应移动Ad Hoc网络特点的事件重构算法。该算法扩展了订阅转发方法,将订阅重构消息转发范围限制在重构路径上,有效避免了订阅冲突,提高重构效率。实验结果表明,该算法缩短了订阅重构时间,且性能受网络规模影响较小。