一种基于数据流分析的故障序列生成方法

故障注入是一种测评容错机制的有效方法,它通过有意识地向目标系统引入故障来加速测试容错机制的试验过程.目前大多数故障注入实验中采用的故障序列都是通过随机抽样获取的,容易造成故障潜伏,从而导致容错机制的评测结果不准确.本文提出一种基于数据流分析的故障序列生成方法.提出<故障注入位置,故障注入时间,故障类型,故障掩码>的单粒子故障模型.在此基础上,通过数据流活跃变量分析计算得出故障注入位置属性,以及定值-引用分析确定了故障注入时间属性.并以PowerPC8548处理器和它对应的Trace模拟器为实验平台,验证了该故障序列生成方法具有90%以上的失效加速比,较好地解决了故障潜伏问题.     

一种基于中间件的容错系统的研究与设计

随着硬件容错技术的成熟，软件容错技术成为提高系统可靠性的热点问题。直接开发容错应用是非常困难的，鉴于中间件为应用系统提供了良好的开发环境，该文研究和设计了一个基于中间件的容错系统模型，提出了一种新的节点容错结构构造方法，为解决冗余、失效检测和恢复等容错的关键技术问题形成了一套较完整的解决方案。采用马尔科夫过程求出系统的可靠度，验证了系统设计的合理性和可靠性。     

The impact of Nintendo Wii to physical education students' balance compared to the traditional approaches

The purpose of this study was to determine whether there is a difference between an exergame-based and a traditional balance training program, in undergraduate Physical Education students. Thirty two third-year undergraduate students at the Democritus University of Thrace were randomly divided into two training program groups of 16 students each, a traditional and a Nintendo Wii group. The two training program groups performed a specific balance program for 8 weeks, two times per week, and 24 min per session. The Nintendo Wii group used the interactive games Wii Fit Plus of the Nintendo Wii console, as a training method to improve their balance, while the traditional group used an exercise program with mini trampoline and inflatable discs. Before and after the completion of the eight-week balance program, participants completed a single leg static balance assessment for both limbs on the Biodex stability system. Two-way analyses of variance (ANOVAs), with repeated measures on the last factor, were conducted to determine effect of training program groups (traditional, Nintendo Wii) and measures (pre-test, post-test) on balance test indices (SI, API, and MLI). Where initial differences between groups were verified, one-way analyses of covariance (ANCOVAs) were applied. Analysis of the data illustrated that both groups demonstrated an improvement in SI, API and MLI mean scores for the right and the left limp as well. Conclusively, findings support the effectiveness of using the Nintendo Wii gaming console as an intervention for undergraduate Physical Education students, and specifically, its effects on physical function related to balance competence.     

一种支持容错的任务并行程序设计模型

任务并行程序设计模型已成为并行程序设计的主流,其通过发掘任务并行性来提高并行计算机的系统性能.提出一种支持容错的任务并行程序设计模型,将容错技术融入到任务并行程序设计模型中,在保证性能的同时提高系统可靠性.该模型以任务为调度、执行、错误检测与恢复的基本单位,在应用级实现容错支持.采用一种Buffer-Commit计算模型支持瞬时错误的检测与恢复;采用应用级无盘检查点实现节点故障类型永久错误的恢复;采用一种支持容错的工作窃取任务调度策略获得动态负载均衡.实验结果表明,该模型以较低的性能开销提供了对硬件错误的容错支持.     

Parallel C语言级容错机制的设计与实现

大规模异构众核计算机系统具有计算能力强、性能功耗比高等突出优点,已成为超级计算机的发展方向,但其复杂的异构结构和庞大的系统规模,也使系统的可用性面临巨大挑战,因此研究面向大规模异构众核系统的轻量级容错技术具有重要意义。针对传统基于检查点的系统级容错开销过大的问题,在Parallel C语言中设计并实现了故障局部感知的轻量级降级、编译指导与自动分析的检查点等语言支持的容错机制,兼顾了好用性和高效性。局部故障感知的轻量级降级结合动态任务调度框架实现,支持众核系统,可扩展到百万以上并行规模;编译指导与自动分析的检查点通过程序员插入简单的编译指示,由编译器进行分析,提示不需要保留的数据,可有效降低保留恢复的数据量。神威太湖之光超级计算机上的测试数据表明,两种容错措施相对于传统容错方法效果良好,轻量级降级的容错开销小于1%,相对于传统回卷容错方法单次故障执行时间可减少3.5%以上,编译指导与自动分析的检查点在典型应用中最多可将保留量降低至1/10,具有很好的实用性。     

免疫机器人的仿生计算与控制

传统的移动机器人研究一般假设环境是安全的，为了增强机器人在危险、变化的环境中适应无人作业的能力，提高机器人对外界干扰、攻击和破坏的抵抗力、容错力和免疫力，提出了危险环境的自体／异体建模方法和免疫机器人的仿生计算模型与控制方法．模仿生物免疫系统，构建机器人的免疫计算模型和免疫控制结构，实现类似于生物免疫系统的自体／异体检测、辨别、学习和修复及鲁棒性、免疫性等功能．免疫机器人技术用来检测、识别和预报危险、变化的环境，检测并修复机器人的正常状态，实现恶劣环境中机器人仿生控制，具有重要的理论创新意义、明显的技术创新价值和可观的应用前景．     

动态资源感知的并行化模糊测试框架

针对现有的并行模糊测试在测试效率、资源利用率以及异常处理上的局限性,本文围绕测试资源的生成、使用及容错三个方面提出了一种动态资源感知的系统化解决方案。针对测试环境在大规模和多场景两个维度快速搭建的需求,提出一种基于云平台的动态构建方法,加快测试环境部署,提高有效fuzz时间;针对并行模糊测试中资源利用率低的问题,提出一种多层次并行度动态调整的资源配置策略,优化整体测试资源配置并提高单机负载;针对大规模并行测试中节点易发生故障的问题,提出基于优先级调度的容错处理方法。最后,本文设计并实现了一个基于四级流水线并行处理结构的通用模糊测试框架。实验证明,该框架能够有效提高并行模糊测试的测试效率和资源利用率,实现系统的有效容错。     

RB-Raft:一种抗拜占庭节点的Raft共识算法

针对Raft算法无法抵抗拜占庭节点的攻击和日志易窜改等问题,设计了一种抵抗拜占庭节点的RB-Raft（resist Byzantine-Raft）算法。首先采用哈希链的方式对每一块日志进行迭代哈希处理,通过动态验证机制对日志进行验证,使得对leader节点的恶意行为具有一定的容错率,解决了日志伪造与验证的问题。其次,提出基于门限加密的遗书机制,使得candidate节点拉取选票具有合法性,防止拜占庭节点随意拉取选票更换leader节点的攻击,解决了拜占庭节点影响系统一致性的问题。实验结果表明,提出的RB-Raft算法具有抗拜占庭节点的能力,其日志识别率可以达到100%。同时,相比PBFT,该算法共识时延降低了53.3%,并且吞吐量提高了61.8%。其适用于在不可信联盟链中进行共识。     

Fault tolerance in Interbus-S standard

The paper deals with the fault tolerance in the Interbus-S, one of the most used FieldBus communication systems. Industrial environments are often featured by critical processes to be controlled. For this reason, the use of a FieldBus to convey information on which these processes are based, requires the presence of fault tolerance mechanisms able to recover a fault in the communication system on its occurrence. In the paper, the authors will highlight the vulnerability of the Interbus-S to fault occurrence in a particular communication node, the Master, foreseen by the Interbus-S standard to distribute the available bandwidth to the control devices connected to the communication system. Finally, the authors will present a protocol extension that allows the whole communication system to continue working after the occurrence of a fault in the Master. The main feature of the proposal is its full compatibility with the Interbus-S standard, as it will be shown in the paper.     

FTRP: a new fault tolerance framework using process replication and prefetching for high-performance computing

As the scale of supercomputers rapidly grows, the reliability problem dominates the system availability. Existing fault tolerance mechanisms, such as periodic checkpointing and process redundancy, cannot effectively fix this problem. To address this issue, we present a new fault tolerance framework using process replication and prefetching (FTRP), combining the benefits of proactive and reactive mechanisms. FTRP incorporates a novel cost model and a new proactive fault tolerance mechanism to improve the application execution efficiency. The novel cost model, called the ‘work-most’ (WM) model, makes runtime decisions to adaptively choose an action from a set of fault tolerance mechanisms based on failure prediction results and application status. Similar to program locality, we observe the failure locality phenomenon in supercomputers for the first time. In the new proactive fault tolerance mechanism, process replication with process prefetching is proposed based on the failure locality, significantly avoiding losses caused by the failures regardless of whether they have been predicted. Simulations with real failure traces demonstrate that the FTRP framework outperforms existing fault tolerance mechanisms with up to 10% improvement in application efficiency for common failure prediction accuracy, and is effective for petascale systems and beyond.     

实时容错调度算法的自动模拟系统模型与设计

实时容错技术是实时系统中的关键技术之一,而实时容错调度算法则是实时容错研究领域中需要重点研究的问题.传统的实时容错调度算法的性能模拟是通过手工完成的,如果采用自动模拟方法,可以提高模拟实验的效率和准确性.首先给出一个实时容错调度算法的自动模拟系统模型,该模型定义了自动模拟系统中的关键参数.然后,提出了实时容错调度自动模拟算法.最后,研究了该自动模拟系统的软件结构.文章研究的自动模拟系统具重要的指导意义,可以参考该系统设计其他类型的调度算法的自动模拟系统.该系统的实现可大大节省用于研究实时容错调度算法的时间和费用.     

基于超立方体容错路由算法分析*

基于超立方体的优良的拓扑性质,提出了一个应用于超立方体网络的容错路由算法.该容错路由算法是基于局部信息的,因为路由算法在路由过程中,只需要知道其邻节点的信息,而无须知道其他节点的出错情况.对于给定的源节点和目的节点,路由算法均能够找到一条最优容错路径,并且可以预防死锁.模拟实验结果表明,路由算法所构造的路由路径长度接近于两个节点之间的最优路径长度.     

Materials Breakthrough Could Eliminate Bootups

Topics include a new version of Adobe Flash that streams Internet content directly to TVs; a project that is researching ways to build computers that don't require bootups; an open source, write-once-run-anywhere approach for mobile applications; and injuries caused by the Nintendo Wii game console.     

协同系统中可扩展的动态容错模型研究及实现

针对协同系统的特点以及其对可靠性、实时性和性能等方面的要求，提出了一种可扩展的动态容错模型xDFT（Extensible Dynamic Fault Tolerance Model，xDFT）．本容错模型将容错支持结构和容错机制结合在一起：在本模型中首先定义了一种可扩展的、动态容错支撑结构；基于此，提出了一种容错机制．xDFT模型能够根据系统负载状况设定服务节点的负载阈值，改变服务冗余度，不仅提高了服务效率，而且以一种简单有效的方式实现了负载平衡．     

Improving reliability of cooperative concurrent systems with exception flow analysis

Developers of fault-tolerant distributed systems need to guarantee that fault tolerance mechanisms they build are in themselves reliable. Otherwise, these mechanisms might in the end negatively affect overall system dependability, thus defeating the purpose of introducing fault tolerance into the system. To achieve the desired levels of reliability, mechanisms for detecting and handling errors should be developed rigorously or formally. We present an approach to modeling and verifying fault-tolerant distributed systems that use exception handling as the main fault tolerance mechanism. In the proposed approach, a formal model is employed to specify the structure of a system in terms of cooperating participants that handle exceptions in a coordinated manner, and coordinated atomic actions serve as representatives of mechanisms for exception handling in concurrent systems. We validate the approach through two case studies: (i) a system responsible for managing a production cell, and (ii) a medical control system. In both systems, the proposed approach has helped us to uncover design faults in the form of implicit assumptions and omissions in the original specifications.     

Architectural Support for Fault Tolerance in a Teradevice Dataflow System

The high parallelism of future Teradevices, which are going to contain more than 1,000 complex cores on a single die, requests new execution paradigms. Coarse-grained dataflow execution models are able to exploit such parallelism, since they combine side-effect free execution and reduced synchronization overhead. However, the terascale transistor integration of such future chips make them orders of magnitude more vulnerable to voltage fluctuation, radiation, and process variations. This means dynamic fault-tolerance mechanisms have to be an essential part of such future system. In this paper, we present a fault tolerant architecture for a coarse-grained dataflow system, leveraging the inherent features of the dataflow execution model. In detail, we provide methods to dynamically detect and manage permanent, intermittent, and transient faults during runtime. Furthermore, we exploit the dataflow execution model for a thread-level recovery scheme. Our results showed that redundant execution of dataflow threads can efficiently make use of underutilized resources in a multi-core, while the overhead in a fully utilized system stays reasonable. Moreover, thread-level recovery suffered from moderate overhead, even in the case of high fault rates.     

基于节点导纳矩阵的模拟电路故障诊断

针对模拟电路故障诊断中的容差问题,提出了基于节点导纳矩阵(NAM)的模拟电路故障诊断方法;该方法以NAM为基础,提取被测电路(CUT)的故障特征向量;测试前,用仿真的方法生成被测电路中某一故障对应的故障样本子集,所有类别的故障样本子集构成故障样本集;测试时,测量被测电路的故障特征向量,并根据其与故障样本集中样本的相似性来判断电路发生的故障类型;由于电路的NAM对元件容差不敏感,所以可以很好地克服模拟电路故障诊断中的容差问题;实验结果证明了该方法的有效性。     

无线网络系统的舰船相对组合导航定位

针对现有单舰船组合导航定位技术存在的不足,如过度依赖GPS、差的可靠性和容错性以及缺乏网络系统概念等,将无线网络系统概念引入到舰船组合导航中,从而基于海上智能交通系统（MITS）提出一种新颖的网络舰船相对组合导航定位方法。该方法不再将海上舰船视为MITS中的孤立节点,因此目标舰船可使用来自网络内其它舰船节点的导航估计并采用最优分布式加权融合来改善自身的组合导航定位估计性能。与现有的单舰船组合导航方法相比,新方法具有更好的导航估训‘精度、更好的稳定性和容错性。     

切换系统的同时故障估计与容错控制

当切换系统发生故障时,通常需要依次进行故障诊断和容错控制.为了提高切换系统故障诊断的可靠性和容错控制的及时性,本文提出一种同时故障估计与容错控制方法.针对满足平均驻留时间约束的线性切换系统,首先建立了基于状态观测器的同时故障估计与容错控制器,并将其设计问题转化为了加权H∞性能指标下增广误差系统的多目标求解问题.然后使用平均驻留时间技术和多Lyapunov函数方法设计了故障估计与容错控制器的参数,又通过松弛矩阵方法进一步得到了保守性较低的结果.最后,利用一个例子对本文所提方法进行了仿真,证实了该方法的有效性.     

网格动态容错服务架构研究*

错误的频繁发生已经成为阻碍网格稳健发展和大规模应用的主要障碍之一,网格系统的容错性研究显得尤为重要。根据网格计算的特点,提出了网格环境下的特殊容错需求;结合用户的服务质量要求,建立了包括网格错误检测与网格错误管理的动态容错服务架构,阐述了错误检测服务与错误管理服务的组织结构、各组成模块的具体功能;最后,给出了一个完整的容错服务实现过程。