共查询到18条相似文献,搜索用时 85 毫秒
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SHA-1算法的HDL设计与仿真 总被引:1,自引:0,他引:1
随着宽带网络和数字视频的飞速发展,如何加强对数据内容的保护成为迫切需要解决的问题.HDCP是一种目前最有效的版权保护协议.它正是采用了SHA-1算法来验证信息传输的完整性.基于HDL语言的硬件设计方法,可以方便地设计硬件电路,建立SHA-1的算法模型,包括码流填充过程和压缩计算过程.用Veriiog HDL描述的电路,其综合结果可通过仿真验证.采用电路结构设计的SHA-1功能模块,简洁高效,可方便地在可编程逻辑器件中实现,并且已在多个嵌入式系统的设计中得到了应用和验证. 相似文献
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基于FPGA的SHA-256算法实现 总被引:1,自引:1,他引:1
本文分析了SHA-256算法的基本工作流程,对算法硬件实现的关键路径进行了优化设计,讨论了几个关键模块的设计方案。最后给出了基于Altera公司的CYCLONE系列FPGA的实现结果。 相似文献
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DRM系统的SHA256算法设计及FPGA实现 总被引:1,自引:1,他引:1
介绍了一种适于DRM系统的SHA-256算法和HMAC算法,给出了在FPGA上实现SHA256算法和HMAC算法的一种电路设计方案,并对算法的硬件实现部分进行了优化设计,给出了基于Altera公司的StratixⅡ系列的FPGA的实现结果。 相似文献
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针对现有的哈希算法硬件架构仅实现少量几种算法的问题,设计了一种可实现SM3,MD5,SHA-1以及SHA-2系列共7种哈希算法的可重构IP,以满足同一系统对安全性可选择的需求。通过分析各哈希算法及其运算逻辑的相似性,该设计最大化地重用加法器和寄存器,极大地减少了总的实现面积。此外,该设计灵活可配,可以对内存直接存取。以Altera的Stratix II为FPGA目标器件,其最高频率可达100 MHz,总面积较现有设计减少26.7%以上,且各算法单位面积吞吐率均优于现有设计。 相似文献
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随着计算机和互联网络技术的迅速发展,电子数据鉴定的结论成为具有证据力的法定证据之一,文中介绍了电子取证中基于SHA-256算法的磁盘复制审计系统的设计与实现,在分析SHA-256算法的基础上,利用FPGA芯片实现了基于SHA-256算法的磁盘复制审计系统,提出了实现磁盘复制和生成SHA-256哈希值一种电路设计方案;利用SHA-256算法对DMA传输方式中的CRC校验码进行计算得到磁盘数据摘要,从而保证了采集数据的一致性,并且整个复制过程必须是可审计的;最后讨论了基于A1tera公司生产的StratixⅡ系列FPGA的实现结果。 相似文献
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针对当前哈希函数算法标准和应用需求不同的现状,以及同一系统对安全性可能有着不同的要求,采用可重构的设计思想,在对SHA-1、SHA-256、SHA-512三种哈希函数的不同特征进行深入分析的基础上,总结归纳出统一的处理模型。根据不同的要求,每一种SHA(SHA-1、SHA-256、SHA-512)系列哈希函数都可以单独灵活地执行。使用流水线,并在关键路径进行加法器的优化,提高了算法的吞吐率。并且使用效能比的概念,与M3服务器对比,可重构平台的效能比比通用服务器高很多。 相似文献
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Keccak自2012年被宣布为新一代Hash函数标准SHA-3后受到密码学界的高度关注,成为当前Hash函数研究的热点。文中给出了SHA-3轮函数中ρ、π和χ三个变换的逆变换。ρ变换只在同一道内沿z轴正向循环移位,故依据其移位距离表沿z轴负方向移位同样距离即得到其逆变换ρ-1;π变换依赖于GF(5)上一个2阶变换矩阵,利用高斯消元法对此方阵求逆可得到其逆矩阵,也即得到了π变换的逆变换;χ变换是SHA-3轮函数中唯一的非线性变换,首先列出χ变换的真值表,然后通过真值表推导得出了其逆变换χ-1的布尔函数表达式。基于ρ^-1、π^-1和χ^-1,可利用中间相遇攻击的思想构造差分路径对SHA-3进行攻击,通过消息修改技术使差分路径以概率1通过χ-1,能够大大提高攻击成功的概率。 相似文献
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Athanasios P. Kakarountas Haralambos Michail Athanasios Milidonis Costas E. Goutis George Theodoridis 《The Journal of supercomputing》2006,37(2):179-195
Hash functions are special cryptographic algorithms, which are applied wherever message integrity and authentication are critical.
Implementations of these functions are cryptographic primitives widely used in common cryptographic schemes and security protocols
such as Internet Protocol Security (IPSec) and Virtual Private Network (VPN). In this paper, a novel FPGA implementation of
the Secure Hash Algorithm 1 (SHA-1) is proposed. The proposed architecture exploits the benefits of pipeline and re-timing
of execution through pre-computation of intermediate temporal values. Pipeline allows division of the calculation of the hash
value in four discreet stages, corresponding to the four required rounds of the algorithm. Re-timing is based on the decomposition
of the SHA-1 expression to separate information dependencies and independencies. This allows pre-computation of intermediate
temporal values in parallel to the calculation of other independent values. Exploiting the information dependencies, the fundamental
operational block of SHA-1 is modified so that maximum operation frequency is increased by 30% approximately with negligible
area penalty compared to other academic and commercial implementations. The proposed SHA-1 hash function was prototyped and
verified using a XILINX FPGA device. The implementation’s characteristics are compared to alternative implementations proposed
by the academia and the industry, which are available in the international IP market. The proposed implementation achieved
a throughput that exceeded 2,5 Gbps, which is the highest among all similar IP cores for the targeted XILINX technology. 相似文献
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This paper presents a compact and unified hardware architecture implementing SHA-1 and SHA-256 algorithms that is suitable for the mobile trusted module (MTM), which should satisfy small area and low-power condition. The built-in hardware hash engine in a MTM is one of the most important circuit blocks and dominates the performance of the whole platform because it is used as a key primitive to support most MTM commands concerning to the platform integrity and the command authentication. Unlike the general trusted platform module (TPM) for PCs, the MTM, that is to be employed in mobile devices, has very stringent limitations with respect to available power, circuit area, and so on. Therefore, MTM needs the spatially optimized architecture and design method for the construction of a compact SHA hardware. The proposed hardware for unified SHA-1 and SHA-256 component can compute a sequence of 512-bit data blocks and has been implemented into 12,400 gates of 0.25 μm CMOS process. Furthermore, in the processing speed and power consumption, it shows the better performance in comparison with commercial TPM chips and software-only implementation. The highest operation frequency and throughput of the proposed architecture are 137 MHz and 197.6 Mbps, respectively, which satisfy the processing requirement for the mobile application. 相似文献
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对哈希算法SHA-1的分析和改进 总被引:2,自引:0,他引:2
研究了哈希算法的相关问题,对常用哈希算法SHA—1从安全性和运算效率方面进行了较深入分析,并由此提出了对该算法的几点改进,使改进后的算法在安全性及运算效率方面较原算法均有所提高。同时还提出了一种安全散列值的计算方法。 相似文献
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Successful attacks against the two most commonly used cryptographic hash functions, MD5 and SHA-1, have triggered a kind of feeding frenzy in the cryptographic community. Many researchers are now working on hash function attacks, and we can expect new results in this area for the next several years. This article discusses the SHA-1 attack and the US National Institute of Standards and Technology's (NIST's) plans for SHA-1 and hash functions in general. 相似文献