可重配置处理器的体系结构级功耗模型与分析

按照可重配置处理器的体系结构建立并实现功耗模型;模型对处理器的电路级特性进行抽象,基于体系结构级属性和工艺参数进行静态峰值功耗估算,基于性能模拟器进行动态功耗统计,并实现三种条件时钟下的门控技术;可重配置处理器与超标量通用微处理器相比,在性能方面获得的平均加速比为3.59,而在功耗方面的平均增长率仅为1.48;通过实验还说明采用简单的CC1门控技术能有效地降低可重配置系统的功耗和硬件复杂度;该模型为可重配置处理器低功耗设计和编译器级低功耗优化研究奠定了基础。     

支持动态可重构硬件透明编程的预配置调度

面向微处理器和可编程器件加速器的混合异构多核体系结构的可重构计算环境,采用程序员熟悉的函数描述格式,在运行时根据软硬件划分的结果,动态实现到软件函数实体代码或者硬件函数实现电路的连接。为降低重配置开销,提高系统性能,统计了各个硬件函数的调用次数和次序,并结合其运行时间和硬件面积等信息,设计了一种预配置算法,尽量使配置和计算能够重叠处理,从而缩短系统的整体运行时间,获得更大性能加速。     

基于Agent的入侵检测系统体系结构设计

提出并深入研究了一种基于智能体技术的入侵检测系统的体系结构。该体系结构是一种混合形结构，利用基于主机和基于网络的数据源，同时使用异常检测技术和误用检测技术。该体系结构中还引入数据挖掘的思想，利用数据挖掘技术从安全审计数据中提取关键的系统特征属性，根据这些属性生成安全审计数据的分类模型用于入侵检测，使IDS自动适应复杂多变的网络环境。     

分布式可重配置航空测控系统设计与实现

通用化、小型化、高可靠性、使用便捷是对大型军用复杂武器装备外场保障设备的通用要求;近年来,随着网络技术、嵌入式计算机技术特别是"可重构计算"技术的发展,可重配置的嵌入式测控系统开发技术成为当前研究的一个热点;文章对该项技术进行了深入研究,并结合飞机子系统外场测试的实际情况,提出并设计实现了一种分布式可重配置航空测控系统;与传统的集中控制测试系统相比较,该系统的体积小、重量轻,使用方便,通过可重配置技术使得测控系统可适应不同的测试需求;该系统的设计实现对军用复杂武器装备外场检测设备设计具有很好的借鉴意义。     

基于代理的网络入侵检测的研制

入侵检测系统可以系统或网络资源进行实时检测，及时发现闯入系统或网络的入侵者，也可预防合法用户对资源的误操作，它是P^2DR(Policy Protection Detection Response，简称P^2DR）安全模型的一个重要组成部分。本文首先介绍了入侵检测系统的研究难点与目前存在的问题，然后重点介绍了我们所研制的基于代理的网络入侵检测系统的体系结构，总体设计与实现，关键技术以及系统的特色。目前该系统在入侵检测系统的体系结构，入侵检测技术、响应与恢复策略，分布式代理（Agent）技术，基于代理的入侵检测知识等方面有创新和突破。     

基于智能的分布式网络入侵检测系统

针对现有入侵检测系统存在系统平台的异构性、入侵数据分析的智能性、面临新的入侵方法时的适应性,以及网络配置发生变化时的可扩展性等方面的不足和问题,本文提出了一个新的结合:CORBA方法和数据挖掘的网络入侵检测系统模型,并详细讨论了该模型的体系结构和工作过程.     

Snort体系结构的研究与分析

剖析了开源入侵检测工具Snort的体系结构及其工作配置模式,为中小型网络配置入侵检测系统提供了可行的解决方案.     

基于Snort的分布式入侵检测系统应用研究

本文首先分析了Snort入侵检测防护体系结构,然后设计与实现了以Snort为核心的分布式入侵检测系统(DIDS),并将其应用到一个实验局域网中。再根据网络实验环境,制定检测策略。并依据检测策略,配置和调整Snort,定制和编写网络实验环境的规则。最后分析了该分布式入侵检测系统在网络实验局域网中运行的实验结果。     

一种基于网络处理器的入侵检测系统

针对目前入侵检测系统的处理速率远远不能满足网络的高速发展，通过对现有IDS的体系结构和算法进行重新设计，提出了一种新的网络入侵检测体系结构。新的体系结构采用网络处理器在网络底层实现数据的采集与分析，提高了IDS的运行速度和效率，能较好地适应高速网络环境下的入侵检测。     

入侵检测系统的应用体系结构

在入侵检测系统中．入侵检测技术和应用体系结构是紧密联系的。由应用体系结构的重要性．可得出以下结论：(1)采用好的入侵检测技术是不完整的．合适的应用体系结构才能让入侵检测技术的功能得到发挥(2)尤其是网络应用环境中的入侵检测系统．面对健壮性．扩展性、可配置性,适应性、全局检测性和效率等要求．更需要着重考虑应用体系结     

Energy efficient processing of motion estimation for embedded multimedia systems

Visual sensor networks require low power compression techniques of large amount of video data in each camera node due to the energy-constrained and bandwidth-limited environments. In this paper, energy-efficient architecture for Variable Block Size Motion Estimation is proposed to fully utilize dynamic partial reconfiguration capability of programmable hardware fabric in distributed embedded vision processing nodes. Partial reconfiguration of FPGA is exploited to support run-time reconfiguration of the proposed modular hardware architecture for motion estimation. According to the required search range, hardware reconfiguration is performed adaptively to reduce the hardware resources and power consumption. A reconfigurable ME ranging from simple 1-D to a complex 2-D Sum of Absolute Differences (SAD) array to perform full search block matching is selected in order to support different search window size. The implemented scalable SAD array can provide different resolutions and frame rates for real time applications with multiple reconfigurable regions.     

Embedding of a real time image stabilization algorithm on a parameterizable SoPC architecture a chip multi-processor approach

Highly regular multi-processor architectures are suitable for inherently highly parallelizable applications such as most of the image processing domain. Systems embedded in a single programmable chip platform (SoPC) allow hardware designers to tailor every aspect of the architecture in order to match the specific application needs. These platforms are now large enough to embed an increasing number of cores, allowing implementation of a multi-processor architecture with an embedded communication network. In this paper we present the parallelization and the embedding of a real time image stabilization algorithm on a SoPC platform. Our overall hardware implementation method is based upon meeting algorithm processing power requirements and communication needs with refinement of a generic parallel architecture model. Actual implementation is done by the choice and parameterization of readily available reconfigurable hardware modules and customizable commercially available IPs (Intellectual Property). We present both software and hardware implementation with performance results on a Xilinx SoPC target.     

Dynamically reconfigurable hardware-software architecture for partitioning networking functions on the SoC platform

We present an issue of the dynamically reconfigurable hardware-software architecture which allows for partitioning networking functions on a SoC (System on Chip) platform. We address this issue as a partition problem of implementing network protocol functions into dynamically reconfigurable hardware and software modules. Such a partitioning technique can improve the co-design productivity of hardware and software modules. Practically, the proposed partitioning technique, which is called the ITC (Inter-Task Communication) technique incorporating the RT-IJC² (Real-Time Inter-Job Communication Channel), makes it possible to resolve the issue of partitioning networking functions into hardware and software modules on the SoC platform. Additionally, the proposed partitioning technique can support the modularity and reuse of complex network protocol functions, enabling a higher level of abstraction of future network protocol specifications onto the SoC platform. Especially, the RT-IJC² allows for more complex data transfers between hardware and software tasks as well as provides real-time data processing simultaneously for given application-specific real-time requirements. We conduct a variety of experiments to illustrate the application and efficiency of the proposed technique after implementing it on a commercial SoC platform based on the Altera’s Excalibur including the ARM922T core and up to 1 million gates of programmable logic.     

一种可重构以太网数据包解析器中可重构单元的设计

不停变化的网络协议标准和用户定制化网络业务需求要求交换机硬件具有更高的灵活性。在此背景下,提出了一种能够通过软件编程定义协议解析规则的以太网交换机芯片数据包解析器基本处理单元,具有高性能且高灵活性的优点,通过灵活配置硬件解析逻辑和查找表内容,定义对数据包包头内容的提取、查找、匹配、动作等解析过程,从而支持对不同种类的协议解析任务,其由2类基本结构的串联或并联组合而成,这样可以根据需要进行硬件资源裁剪。基于该可重构基本处理单元,可以构成可重构报文解析器,支持自定义协议及未知协议的解析。主要介绍了该可重构基本处理单元的结构,并介绍了基于该基本处理单元的解析器架构的实现方法。采用40 nm工艺综合后的评估结果显示,该基本单元电路最高工作时钟频率可以达到240 MHz,基于该基本处理单元结构实现的支持4层常用以太网协议解析的解析器每秒可处理2.4亿个数据包。该可重构基本处理单元所用存储资源共计87.98 Kb,设计规模约147万门。     

可重构密码处理结构中重构机制及对性能的影响

重构机制对可重构密码处理系统的性能有着重要的影响,该文从全局、局部、静态、动态几方面提出了流水化可重构密码处理结构中重构机制的分类,给出了各种机制的吞吐率和延迟公式,并分析了几种机制的性能和实现代价,最后给出了在采用局部动态重构机制的可重构密码处理结构中密码处理的性能。     

The MORPHEUS Heterogeneous Dynamically Reconfigurable Platform

Reconfigurable computing offers a wide range of low cost and efficient solutions for embedded systems. The proper choice of the reconfigurable device, the granularity of its processing elements and its memory architecture highly depend on the type of application and their data flow. Existing solutions either offer fine grain FPGAs, which rely on a hardware synthesis flow and offer the maximum degree of flexibility, or coarser grain solutions, which are usually more suitable for a particular type of data flow and applications. In this paper, we present the MORPHEUS architecture, a versatile reconfigurable heterogeneous System-on-Chip targeting streaming applications. The presented architecture exploits different reconfigurable technologies at several computation granularities that efficiently address the different applications needs. In order to efficiently exploit the presented architecture, we implemented a complete software solution to map C applications to the reconfigurable architecture. In this paper, we describe the complete toolset and provide concrete use cases of the architecture.     

GF(2)域上FSR+NLF类序列密码可重构处理结构设计

讨论了FSR+NLF类序列密码的可重构处理结构设计,包括总体结构设计、可重构FSR结构设计、可重构NLF结构设计以及互连网络结构设计。采用该结构的密码运算单元可以根据需要实现多种此娄序列密码,具有结构简单、可扩展、运行速度高等特点。     

An instruction-level distributed processor for symmetric-key cryptography

Efficient implementation of block ciphers is critical toward achieving both high security and high-speed processing. Numerous block ciphers have been proposed and implemented, using a wide and varied range of functional operations. Existing architectures such as microcontrollers do not provide this broad range of support. Therefore, we will present a hardware architecture that achieves efficient block cipher implementation while maintaining flexibility through reconfiguration. In an effort to achieve such a hardware architecture, a study of a wide range of block ciphers was undertaken to develop an understanding of the functional requirements of each algorithm. This study led to the development of COBRA, a reconfigurable architecture for the efficient implementation of block ciphers. A detailed discussion of the top-level architecture, interconnection scheme, and underlying elements of the architecture will be provided. System configuration and on-the-fly reconfiguration will be analyzed, and from this analysis, it will be demonstrated that the COBRA architecture satisfies the requirements for achieving efficient implementation of a wide range of block ciphers that meet the 622 Mbps ATM network encryption throughput requirement.     

基于Snort的入侵检测系统在校园网的应用

面对越来越复杂的互联网络环境,传统安全体系受到严重威胁,入侵检测系统(Intrusion Detection System,IDS)已经成为安全系统中重要的组成部分。该文简要地介绍了入侵检测系统的分类、原理和系统结构。并以著名开源NIDS Snort为例,设计并实现了一个校园网入侵检测系统。     

配置流驱动计算体系结构指导下的ASIP设计

为了兼顾嵌入式处理器设计中的灵活性与高效性,提出配置流驱动计算体系结构.在体系结构设计中将软/硬件界面下移,使功能单元之间的互连网络对编译器可见,并由编译器来完成传输路由,从而支持复杂但更为高效的互连网络.在该体系结构指导下,提出一种支持段式可重构互连网络的专用指令集处理器(ASIP)设计方法.该方法应用到密码领域的3类ASIP设计中表明,与简单总线互连相比,在不影响性能的前提下,可平均节约53%的互连功耗和38.7%的总线数量,从而达到减少总线数量、降低互连功耗的目的.