一种组合电路内建自测试的改进方法

对组合电路的测试提出了一种将确定性测试生成方法与内建自测试相结合的设计方案;设计实现了利用D算法生成的测试矢量和伪随机测试序列生成电路共同构成测试矢量生成模块,利用内建自测试方法完成可测性设计,并将两者结合得出组合电路内建自测试的改进方法;分析与实验结果表明,该方法能减少系统硬件占用,同时具有测试向量少、故障覆盖率高的特点。     

一种基于动态可测性测度的快速识别逻辑冗余故障的方法—DRFM

在测试生成之前,借助可测性分析方法,以线性时空开销识别数字电路的冗余故障是个至今尚未解决的问题.本文在文献[8,9]的四值动态代价分析的基础上,首次采用动态相关信号模型,提出了动态约束四值测度方法DRFM.DRFM能精确描述实用电路中常见的冗余故障,它识别一个冗余故障所需的时间为电路门数的线性增长函数.     

基于IEEE1149.4标准的K节点故障诊断方法研究

IEEE1149．4标准为解决数模混合电路的边界扫描测试提供了有效的方法；在IEEE1149.4标准所提出的模拟互连测试结构的基础上，结合K节点故障的可测性原则和测试节点选择方法，实现对常规的复杂无源模拟电路网络进行符合IEEE1149.4标准的可测性设计进行故障诊断，并通过实例验证该方法的有效性。     

一种新的缩短自测试序列长度的方法

本文建立在逻辑电路内部自测试的基础上，提出了一种新的缩短伪随机测试序列长度的方法。文中首先找到了最难测故障在电路中的分布，建立了对应于最难测故障的电路模型，然后用线性反馈移位寄存器对这些电路模型的输出信号进行压缩，通过分析压缩后的特征码，得出最难测故障的测试长度。最后利用电路的原始输入概率与测试长度之间的关系，提出了一种缩短测试序列长度的算法，求出了最短的测试长度与最佳的输入概率。     

RRTL：一种缩短随机测试长度的方法

本文提出了一种新的缩短随机测试序列长度的方法－ＲＲＴＬ法，它是在找到电路中难测故障分布的基础上，通过对电路的初始输入施加量佳概率的信号，使得最难测故障的测试长度变为极小值，因而也就大大缩短了测试时间。     

基于多配置LFSR的测试生成结构设计

针对内建自测试技术中传统的测试生成故障覆盖率过低、硬件开销过大等缺点,提出了一种多配置LFSR的混合测试矢量生成结构,结构利用矩阵理论先后对随机性矢量和确定性矢量进行反馈网络的配置;针对确定性矢量的生成,提出了一种反馈配置解的寻优算法,在一定程度上减少了硬件开销,因结构生成的混合测试矢量可以同时检测出被测电路中的随机矢量可测性故障和抗随机性故障,进而保证了测试故障覆盖率。最后,通过实例和对几种综合基准电路的测试,验证了该方案的可行性。     

基于伪随机测试的模数混合信号内建自测试法

利用伪随机序列作为测试激励,通过计算输入输出的互相关函数得到K维特征空间,在特征空间的基础上进行分析,判别电路有无故障,实验证明该方法简单可行,且提高了测试的效率和正确性,适用于模拟及混合信号测试,适用于混合信号电路的内建自测试（BIST）。     

组合电路随机测试的一种新方法

本文在随机测试的基础上提出了逆随机测试（ART）的新概念，在该测试序列的集合中各测试码之间的海明距离为尽可能的大，这样可以使不同的测试码检测到更多不同的故障，从则提高了测试效率和故障覆盖率。本文给出了构造逆随机测试序列（ARTS）的详细过程，并且严格证明了该序列的高效和正确性，同时还给出了用Benchmark和其它电路作为例子的实验结果。     

IIR滤波器的测试及可测性设计

基于加法器测试生成,提出了无限脉冲响应(IIR)滤波器的一种通用可测性设计、测试方案.在测试模式下,通过切断IIR滤波器中的反馈回路提高了该设计的可测性.通过复用原电路中的部分寄存器和加法器来提高其可测性,降低了额外的测试硬件面积开销.该方法能在真速下高效地侦测到IIR滤波器基本组成单元内的任意固定型组合失效,没有降低电路性能.     

GTPP—一种全局测试点插入算法

本文提出了一个全局测试点插入算法。该算法在可测性设计以前首先分析了电路的可测性，得到测试点候选集，该集合中每一个点都是对该电路的可测性可能有很大改进的测试点。文中首先采用选择跟踪的思想得到全局测试点插入的初始界限，然后将测试点插入算法形式化为一个要枝界限的问题，得到了一种全局的测试插入结果，文中的算法是基于ＳＣＴＭ测试提出来的。     

VFSim: Concurrent Fault Simulation at Register Transfer Level

VLSI testing is being pushed to the high-level based technology. In this paper a Verilog Register transfer level Model (VRM) for integrated circuits is proposed. The model provides a text format file, which is convenient and more practical for developing succeeding Register Transfer Level (RTL) test tools, such as fault simulation, test pattern generation and so forth. Based on the VRM, an RTL concurrent fault simulation approach is presented. After RTL fault models and super faults defined, the concurrent fault simulation algorithm is given. The corresponding RTL concurrent fault simulator, VFSim, was implemented. The initial experiments show that the RTL fault simulator is efficient for VLSI circuits.     

Generating tests for delay faults in nonscan circuits

A delay test method that allows any sequential-circuit test generation program to produce path delay tests for nonscan circuits is presented. Using this method, a given path is tested by augmenting the netlist model of the circuit with a logic block, in which testing for a certain single stuck-at fault is equivalent to testing for a path delay fault. The test sequence for the stuck-at fault performs all the necessary delay fault test functions: initialization, path activation, and fault propagation. Results on benchmarks are presented for nonscan and scan/hold modes of testing     

时序电路测试向量融合算法

时序电路的测试序列通常由各个单故障的测试向量组成.为了减少测试时间和功耗,提出2种测试向量融合算法.借助融合灵活性的概念,2种算法按不同的方式对向量序列进行排序,并以融合深度和代价作为评判准则,构建向量的融合过程,最终生成整个电路的测试序列.该算法与已有的Greedy算法时间复杂度相同,但性能更优.在ISCAS89部分电路上的实验结果表明,采用文中算法可使平均性能分别提高4.96%和8.23%.故障仿真结果表明,文中算法的故障覆盖率有少量提高,故障分辨率变化较小.     

同步时序电路测试生成研究

本文分析了固定故障所反映出的状态变换特征，提出状态变换故障模型。基于无复位时序电路，详细研究了有复位的同步电路测试生成问题及在无复位电路中的应用。最后讨论了故障精简以及启发知识在测试过程中的应用。     

Design for Testability for Complete Test Coverage

Some design-for-testability techniques, such as level-sensitive scan design, scan path, and scan/set, reduce test pattern generation of sequential circuits to that of combinational circuits by enhancing the controllability and/or observability of all the memory elements. However, even for combinational circuits, 100 percent test coverage of large-scale circuits is generally very difficult to achieve. This article presents DFT methods aimed at achieving total coverage. Two methods are compared: One, based on testability analysis, involves the addition of test points to improve testability before test pattern generation. The other method employs a test pattern generation algorithm (the FAN algorithm). Results show that 100 percent coverage within the allowed limits is difficult with the former approach. The latter, however, enables us to generate a test pattern for any detectable fault within the allowed time limits, and 100 percent test coverage is possible.     

A generalized fault simulator for combinational logic circuits

A generalized approach to the design of fault simulator using a library of simulation primitives is presented in this paper. A comprehensive set of simulation primitives has been developed using C programming language on the IBM PC. This library of simulation primitives has been used in realizing a fault simulator for automatic test pattern generation in combinational logic circuits. The fault simulator employs a combination of random pattern generation, concurrent fault simulation and the FAN algorithm for generating the complete set of test vectors to cover all the faults in the fault dictionary of the circuit under test. The library of simulation primitives is general enough to facilitate the development of fault simulators using any other test algorithms such as DALG or PODEM.     

Complex phenomena understanding in electricity through dynamically linked concrete and abstract representations

The present study investigates the impact of utilizing virtual laboratory environments combining dynamically linked concrete and abstract representations in investigative activities on the ability of students to comprehend simple and complex phenomena in the field of electric circuits. Forty‐two 16‐ to 17‐year‐old high school students participated in a guided‐inquiry‐based teaching intervention utilizing a virtual laboratory environment and were assigned to three conditions: functional dynamically linked concrete and abstract representations of objects (CA approach), functional concrete representations of objects alone (C approach) and functional abstract representations of objects alone (A approach). All conditions used the same instructor, instructional method and materials. A pretest–post‐test scheme was used to assess the students' conceptual evolution. A repeated measures multivariate analysis of variance of the results indicates that after instruction all groups show a similar significant improvement in comprehending simple phenomena in electric circuits. However, for complex phenomena, the CA approach significantly outperforms the other two. It seems, therefore, that in the field of electric circuits, investigative activities utilizing virtual laboratory environments with dynamically linked concrete and abstract representations of objects may foster enhanced understanding of phenomena with a high degree of complexity for high school students.     

Circular self-test path for FSMs

Circular self test path (CSTP) is an attractive method for automatically transforming sequential circuits generated by automatic synthesis tools into BIST structures. The authors extend this method-making it more suitable for FSMs derived from synthesized control parts-and are integrating it into an industrial design flow supporting testable synthesis. The CSTP approach provides good results in terms of test length and fault coverage in large circuits. It requires substitution of all or some of the flip-flops in the circuit with special cells and their connection to constitute a circular chain. CSTP also has application in industrial environments, and several commercial CAE environments, such as that used by AT&T, now support CSTP as an approach for automatic introduction of BIST in circuits     

Decreasing Test Qualification Time in AMS and RF Systems

The authors of this article illustrate a means to use design models and simulation testbenches to decrease manufacturing test costs. This technique enables test cost optimization early in the RFIC design phase. In this article, we propose a test set optimization and qualification method that targets test application time, cost, and quality while also decreasing the generation time of production tests. Our approach decreases the manufacturing test cost of AMS and RF SoCs by automatically qualifying and optimizing existing test sets. We present a computer-aided test (CAT) tool, Plasma (platform for system qualification with mixed and analog signals), that uses fault injection and a fault simulation technique to perform test qualification and generation. This tool reduces both test time and test equipment cost using a high-level fault model. Our approach relies on the qualification and optimization of a predefined test set. With this article, we show how to reduce the test optimization time by using behavioral modeling and decreasing the number of simulated circuits. This method reduces the number of simulated fault-free models, thanks to a normal estimation.