改进型缓存敏感B+树的研究

在内存数据库中,处理器缓存的失配次数对系统的性能有重要的影响;缓存敏感的索引能减少在做查询操作时产生的缓存失配次数,从而提高系统的性能;传统的设计思路将结点大小等于缓存块大小,认为这样就能使得缓存失配次数减少;但是这样的设计忽略了TLB失配对系统性能的影响;我们提出了一种缓存敏感索引——改进型缓存敏感B＋树（简称MCSB＋树）,它同时兼顾了缓存失配和TLB失配对系统性能的影响。比传统的缓存敏感索引能提供更好的操作性能。     

支持内存数据库索引缓存优化的CST树的设计与实现

针对目前内存数据库中索引缓存失配的问题,在分析了现有内存数据库索引结构基础上,提出了一种缓存敏感T树（CST树）的索引数据结构,详细数据结构描述和操作算法也已给出。通过CST树的缓存次数分析和进行查询、插入等操作性能测试,结果表明CST树能有效减少缓存敏感次数,并且在数据量较小时,CST树的插入、删除速度比T树略慢,而查询速度比T树要快。在数据量较大时,CST树的插入、删除、查询效率都比T树要高。     

内存数据库索引技术研究

内存数据库已经成为了当今数据库研究的热点,而索引能够极大地提高数据库操作的性能.文章介绍了内存数据库发展至今比较成熟的一些索引结构,并在查找时间上对它们进行了对比分析,总结了结构特点和分析数据之后的结论表明,CSS树索引和CSB树索引有着最好的缓存意识,同时还具有很高的查找速度和空间利用率.     

位图连接索引服务机制研究

位图连接索引是数据仓库中一种有效的优化表间连接操作性能的索引机制。在大内存分析处理应用场景下,位图连接索引不仅需要权衡索引的内存和CPU开销,还需要进一步考虑处理器平台所带来的性能收益和数据访问延迟。提出了基于服务的位图连接索引管理机制,其主要特点体现在三个方面：独立于数据库的自管理索引机制;基于存储空间约束的TOP K关键字位图连接索引机制;处理器敏感（processor-conscious）的位图连接索引技术。索引服务将索引从数据库中内置的数据结构变成数据库外的索引服务层,通过对用户查询负载的分析模块和索引服务管理模块改变传统的由数据库管理员人工管理索引的模式,同时借助于协处理器和内存云技术提高索引服务的性能和灵活性。实验测试结果表明,索引服务机制能够有效地提高索引存储和访问效率,在通用GPU的强大并行处理能力的支持下,位图连接索引服务的性能和数据库整体查询处理性能都得到了显著的提升。     

多核处理器环境下内存数据库索引性能分析

从20世纪80年代内存数据库出现时的T树到21世纪初出现的缓存感知的CSS、CSB+树等,都适应了当时的硬件发展趋势,具有一定的性能优势.随着计算机硬件技术的进一步发展,尤其是多核技术的应用与推广,新的多核处理器在提高索引性能的同时又给内存索引结构提出了新的挑战.文中对B+树、T树、CSS树、CSB+树等几个经典的内存索引结构在多核处理器环境下的性能进行了全面的实验测试,对其在多核处理器环境下不同数据输入、不同节点大小等多种情况下的性能构成与差异进行了比较和分析,总结了在多核处理器中影响索引性能的关键因素,为内存索引结构的进一步改进奠定了坚实的基础.     

内存数据库在TPC-H负载下的处理器性能

Ailamaki等人1999年研究了数据库管理系统(database management system,简称DBMS)在处理器上的时间开销分解.此后,相关研究集中在分析DBMS在处理器上的瓶颈.但这些研究工作均是在磁盘数据库DRDBs(disk resident databases)上开展的,而且都是分析DBMS上的TPC-C类负载.然而,随着硬件技术的进步,现代计算机的多级缓存结构(memory hierarchy)在逐渐地"上移".例如,容量越来越大的芯片内缓存(on-chip caches)和芯片外缓存(off-chip caches),容量越来越大的RAM,Flash Memory等等.为此,处理器负载分析的研究工作也应随之"上移".研究内存数据MMDBs(mainmemory resident databases)在计算密集型负载下的处理器行为特性.由于磁盘数据库的主要性能瓶颈是磁盘I/O,因而可以用索引、压缩等技术进行优化;然而,内存数据库的性能瓶颈却在于处理器和内存之间的数据交换.针对这一问题,首先分析了磁盘数据库和内存数据库在TPC-H负载下处理器性能瓶颈的差异,并给出了一些优化建议,提出了通过预取的优化方法.其次,通过实验比较了不同存储体系结构(行存储与列存储)对处理器利用率的差异,并探索了下一代内存数据库体系结构方面的解决方案.此外,还研究了索引结构对处理器多级缓存的影响,并给出了索引的优化建议.最后,提出一个微测试集用于评估内存数据库在DSS(decision support system)负载下处理器的性能及行为特性.研究结果会对运行于下一代处理器上的内存数据库体系结构设计和性能优化提供一定的实验依据.     

一种适应GPU的混合访问缓存索引框架

散列表（hash table）作为一类根据关键码值（key value）提供高效数据访问的数据索引结构,其广泛应用于各类计算机应用中,尤其是在对性能要求极高的系统软件、数据库以及高性能计算领域.在网络、云计算和物联网服务方面,以散列表为核心结构已经成为缓存系统的重要系统组件.然而,随着大规模数据量的大幅度增加,以多核CPU为核心设计散列表结构的系统已经逐渐出现性能瓶颈,亟需进一步改进散列表的高性能和可扩展性.随着通用图形处理器（graphic processing unit,简称GPU）的日益普及以及硬件计算能力和并发性能的大幅度提升,各类以并行计算为核心的系统软件任务在GPU上进行了优化设计并得到可观的性能提升.由于存在稀疏性和随机性,采用现有散列表的并行结构直接在GPU上应用势必会带来高频次的内存访问和频繁的总线数据传输,影响了散列表在GPU上的性能发挥.重点分析了缓存系统中散列表索引的内存访问、命中率与索引开销,提出并设计了一种适应GPU的混合访问缓存索引框架CCHT（cache cuckoo hash table）,提供了两种适应不同命中率和索引开销要求的缓存策略,允许写入与查询操作并发执行,最大程度地利用了GPU硬件的计算性能与并发特性,减少了内存访问与总线传输.通过在GPU硬件上的实现与实验验证,CCHT在保证缓存命中率的同时,性能优于其他用于缓存索引的散列表.     

一种适用于嵌入式数据库的新索引机制

由于嵌入式系统具有内存资源极为有限和处理器速度不高等特点,因此适用于嵌入式数据库的索引机制应在尽量减少内存占用量的基础上进一步提高数据操作的速度.现有的数据库索引机制不能同时满足时空双方面要求,因此本文在传统混合索引机制hybrid-TH的基础上提出一种新索引机制-H-T*-tail,探讨它的基本操作算法并通过具体实验验证其优良的时空性能.     

轻量级缓存策略的关系型数据库全文搜索加强与扩展

针对关系型数据库（RDB）现有的全文搜索方案存在的效率低下、资源占用高的问题，提出一种具有增强式辅助缓存的轻量级关系型数据库全文搜索模型。首先，该模型构建基于Redis的倒排索引，并利用缓存索引缩小搜索范围，从而用内存高效的数据处理能力解决关系型数据库I/O瓶颈，并提升系统整体性能；其次，为保证搜索结果的准确性和时效性，进一步提出索引同步策略，而且设计并实现了增量索引组件来隐藏索引处理细节，从而提高模型的易用性和通用性；最后，对于热点数据提供一种基于访问热度的索引更新机制，以降低倒排索引的内存占用。实验结果表明，所提模型在保证关系型数据库全文搜索响应速度和准确度的前提下，空间资源消耗比MySQL全文索引降低了48.8%～60.9%，比Elasticsearch降低了85.2%～96.2%，证明所提模型在实际应用中可行且有效。     

航天实时内存数据库存取机制MCacheTree的研究

考虑到空间环境探测、空间科学实验所产生的数据时效性比较强,为了对它们进行有效的管理,研究了提高实时性能的索引技术.由于IO速度较慢、外存延迟时间难以预测,实时数据库系统通常采取内存数据库技术.基于此,提出了一种新的适合航天实时内存数据库系统的索引结构:MCacheTree,它将内存缓存和检索树有机地结合起来,并应用延迟写和延迟删除的优化技术,有效地降低了查询时间,提高了实时性能.最后通过实验验证了该设计的高效性.     

CSA-Tree:一种改进的高维主存索引树

主存技术的不断进步,使得主存多媒体数据库的实现成为可能.研究表明,主存多媒体数据库系统性能深受处理器缓存未命中的影响,缓存感知型主存索引是提高数据检索效率的有效手段.针对SA-Tree不适用于主存存取的缺点,提出它的变体CSA-Tree.CSA-Tree利用PCA降维技术,将树的各层节点采用不同的维度表示,这样不仅提高了缓存空间的利用率,还降低了CPU负载,从而提高了索引查询效率.大量实验证明,CSA-Tree在主存环境中具有良好的高维数据检索性能.     

Managing data caches using selective cache line replacement

As processor performance continues to improve, more demands are being placed on the performance of the memory system. The caches employed in current processor designs are very similar to those described in early cache studies. In this paper, a detailed characterization of data cache behavior for individual load instructions is given. It will be shown that by selectively allocating cache lines according the characteristics of individual load instructions, overall performance can be improved for both the data cache and the memory system. This approach can improve some aspects of memory performance by as much as 60 percent on existing executables. This work was supported by National Science Foundation Grants CCR-94-03651, CCR-92-13651, CCR-92-13627, MIP-92-57259, and generous grants from the SUN Microsystems and Tektronix corporations.     

决策树、朴素贝叶斯和朴素贝叶斯树的比较

利用数据挖掘工具Weka,在常态数据集adult上进行实验,从时间、正确率、误差率三个指标对比分析J48（C4．5决策树）,朴素贝叶斯分类器,朴素贝叶斯树（NBTree）三种分类算法．结论为：在内存充足,时间要求不高的情况下,使用朴素贝叶斯树（NBTree）能获得更高的正确率和错误率;J48则是一种折中的方案;朴素贝叶斯分类器完成时间最短,但正确率和错误率为三种算法中最差．     

Using the First-Level Caches as Filters to Reduce the Pollution Caused by Speculative Memory References

High-performance processors employ aggressive branch prediction and prefetching techniques to increase performance. Speculative memory references caused by these techniques sometimes bring data into the caches that are not needed by correct execution. This paper proposes the use of the first-level caches as filters that predict the usefulness of speculative memory references. With the proposed technique, speculative memory references bring data only into the first-level caches rather than all levels in the cache hierarchy. The processor monitors the use of the cache blocks in the first-level caches and decides which blocks to keep in the cache hierarchy based on the usefulness of cache blocks. It is shown that a simple implementation of this technique usually outperforms inclusive and exclusive baseline cache hierarchies commonly used by today’s processors and results in IPC performance improvements of up to 10% on the SPEC CPU2000 integer benchmarks.     

Oracle B＊树索引内部机制及其应用的研究

Oracle数据库应用系统的性能优化是一项系统化的工程,涉及到数据库结构的各个方面。本文从B＊树索引入手,分析了B＊树索引的结构及原理,阐明了如何正确合理地使用B＊树索引及其如何优化数据库系统的性能。     

Probabilistic Prediction of Temporal Locality

The increasing gap between processor and memory speeds, as well as the introduction of multi-core CPUs, have exacerbated the dependency of CPU performance on the memory subsystem. This trend motivates the search for more efficient caching mechanisms, enabling both faster service of frequently used blocks and decreased power consumption. In this paper we describe a novel, random sampling based predictor that can distinguish transient cache insertions from non-transient ones. We show that this predictor can identify a small set of data cache resident blocks that service most of the memory references, thus serving as a building block for new cache designs and block replacement policies. Although we only discuss the L1 data cache, we have found this predictor to be efficient also when handling L1 instruction caches and shared L2 caches.     

用于内存数据库的Hash索引的设计与实现

电信领域已成为数据密集型行业，需要高性能的数据库系统作为支撑系统，基于磁盘的数据库系统不能满足“实时”、“近实时”访问数据库的需求，将数据库核心数据驻留在内存中，可以使用内存数据库来满足需求。Hash索引是数据库系统中广泛使用的索引技术之一，它能够快速地访问数据，易于设计和实现。该文根据内存数据库的特点，为电信网管系统的内存数据库设计并实现了Hash索引。     

Linked instruction caches for enhancing power efficiency of embedded systems

The power consumed by memory systems accounts for 45% of the total power consumed by an embedded system, and the power consumed during a memory access is 10 times higher than during a cache access. Thus, increasing the cache hit rate can effectively reduce the power consumption of the memory system and improve system performance. In this study, we increased the cache hit rate and reduced the cache-access power consumption by developing a new cache architecture known as a single linked cache (SLC) that stores frequently executed instructions. SLC has the features of low power consumption and low access delay, similar to a direct mapping cache, and a high cache hit rate similar to a two way-set associative cache by adding a new link field. In addition, we developed another design known as a multiple linked caches (MLC) to further reduce the power consumption during each cache access and avoid unnecessary cache accesses when the requested data is absent from the cache. In MLC, the linked cache is split into several small linked caches that store frequently executed instructions to reduce the power consumption during each access. To avoid unnecessary cache accesses when a requested instruction is not in the linked caches, the addresses of the frequently executed blocks are recorded in the branch target buffer (BTB). By consulting the BTB, a processor can access the memory to obtain the requested instruction directly if the instruction is not in the cache. In the simulation results, our method performed better than selective compression, traditional cache, and filter cache in terms of the cache hit rate, power consumption, and execution time.     

Characterization and Evaluation of Cache Hierarchies for Web Servers

As Internet usage continues to expand rapidly, careful attention needs to be paid to the design of Internet servers for achieving high performance and end-user satisfaction. Currently, the memory system continues to remain a significant performance bottleneck for Internet servers employing multi-GHz processors. In this paper, our aim is two-fold: (1) to characterize the cache/memory performance of web server workloads and (2) to propose and evaluate cache design alternatives for future web servers. We chose SPECweb99 as the representative web server workload and our entire characterization and evaluation methodology is based on our CASPER simulation framework. We begin by exploring the processor cache design space for single and dual-processor servers. Based on our observations, we then evaluate other cache hierarchy alternatives such as chipset caches, coherence filters and decompressed page stores. We show the sensitivity of these components to basic organization parameters such as cache size, line size and degree of associativity. We also present the performance implications of routing memory requests initiated by I/O devices through these caches. Based on detailed simulation data and its implications on system level performance, this paper shows that chipset caches have significant potential for improving future web server performance.