基于代码压缩方法的低功耗嵌入式系统设计技术研究

低功耗是嵌入式系统设计中的重要约束条件之一．代码压缩能够减小程序目标代码尺寸，减小程序目标代码所占用的存储器空间和通信开销，从而在系统级上降低了系统功耗．本文对指令集裁剪压缩技术、全代码压缩与子代码压缩技术以及基于片上Cache的代码压缩技术等几种比较典型的代码压缩技术的特征进行了讨论和分析．     

嵌入式智能机器人平台研究

针对传统工业机器人采用的封闭式结构的局限性，在Windows CE.NET系统基础上，通过剪裁定制，去除冗余的功能，搭建嵌入式智能机器人平台．该智能机器人系统具有移动机器人需要的主要感知模块，并有丰富的运动控制接口及驱动模块．同时，设计了多传感器数据融合、轨迹规划、运动控制、无线网络通信、图形人机界面等智能机器人的测试软件和应用模块．该智能机器人平台具有模块化、易扩展、可移植、可定制、硬件体积小、功耗低、实时性强、可靠性高等优点．     

高性能微处理器微体系结构级功耗模型及分析

基于Itanium2微处理器体系结构提出单时钟和多时钟域两种基准模型；对处理器的电路级特性进行微体系结构级抽象，建立了参数化的峰值功耗估算模型；提出事件调度算法，实现了多时钟域处理器系统的行为级模拟；以IMPACT工具集作为模拟引擎实现了处理器的动态功耗模拟模型．与其它同类模型Wattch相比，该模型能够支持多时钟系统的模拟，峰值功耗估算精度高了约3％，而模拟速度提高了42％．通过实验说明了多时钟域的功耗特性，在一种多电压和频率环境下，多时钟域处理器的功耗和能量分别降低了21％和38％．该模型可以很好地应用到体系结构级低功耗研究设计．     

一种软件缺陷模式自定制方法

软件缺陷是导致软件不可靠的根本原因,提高软件可靠性的关键在于减少软件缺陷。基于缺陷模式的代码分析技术根据预先设定好的缺陷模式对待测代码进行缺陷分析,这种缺陷分析具有使用简单、查找速度快等优点,是近年来静态代码分析技术中发展比较迅速的新技术。但是目前基于这种分析技术的大多数工具并没有为用户提供足够易用、高效的扩展方式以扩充其缺陷检测能力。本文出了一种支持用户定制语法相关缺陷模式的测试方法及系统,该方法能够让用户根据实际情况需要对缺陷模式进行定制,目的是检测程序代码中是否包含语法相关的缺陷。     

Meta—CASE技术的探讨

Meta－CASE是通过Meta－CASE工具生成CASE工具，形成支持软件开发方法工具集的技术．本文主要就Meta－CASE技术及ToolBuilder技术进行分析和讨论．     

一种谱分析的Matlab与VHDL代码转换方法

本文讨论由Matlab生成VHDL代码的原理,并介绍了利用System Generator及DSP Builder将Simulink模型转换为VHDL代码的方法。这样设计者可以利用Simulink高层次的设计仿真工具进行系统级设计,有助于在设计早期发现错误和应对系统复杂性不断增加的挑战,使用集成转换工具能够方便地进行VHDL代码的生成并进行硬件测试,极大地提高了设计效率。     

电力信息系统软件代码漏洞检测系统的设计与实现

电力信息系统软件代码的自身安全对整个电力信息系统的安全性、稳定性以及可靠性有着举足轻重的影响。为了提高电力信息系统软件代码的安全水平，设计并实现了一套代码漏洞静态检测系统。该系统以代码静态分析技术为基础，支持漏洞检测规则定制、漏洞检测算法与检测引擎扩展以及多线程技术，并通过Java语言编程实现。系统测试结果表明，该系统能够准确、有效地检测出测试程序中的安全漏洞，验证了系统的有效性。     

一种增强的低功耗的嵌入式系统设计

嵌入式系统片上Cache功耗是微处理器的功耗的最主要部分.提出新的低功耗技术,将Filter Cache方法与Loop Table方法相结合,无需增加新的指令,不需要复杂的硬件结构,并可针对具体的应用程序对处理器系统结构进行定制.     

Cache低功耗技术研究

现代微处理器中Cache已经成为不可缺少的重要部件,其功耗约占整个芯片功耗的30%￣60%[1,2]。如何减少Cache的功耗,已成为当今Cache设计者关注的焦点。论文提出了一种基于Cache可重组技术以及数据符号压缩技术的低功耗D-Cache设计方法,其技术关键在于动态调整Cache的组织结构,并且改变Cache-Line中数据的存储方式来降低Cache功耗。     

ADI公司利用Radio Verse技术和设计生态系统简化无线系统设计

<正>Analog Devices,Inc.(ADI),全球领先的高性能信号处理解决方案供应商,最近推出RadioV erse技术和设计生态系统,以便为客户提供集成收发器技术、鲁棒的设计环境和针对特定市场的技术专长,使其无线电设计能够快速从概念变为产品。新生态系统的收发器技术可缩减无线电尺寸、重量和功耗(SWaP),设计环境提供板级支持包、软件和工具来帮助客户简化并加快各种应用的无线电开发,包括无线基础设施、航空航天与防务电子、电子     

Studying the code compression design space – A synthesis approach

Embedded domain has witnessed the application of different code compression methodologies on different architectures to bridge the gap between ever-increasing application size and scarce memory resources. Selection of a code compression technique for a target architecture requires a detailed study and analysis of the code compression design space. There are multiple design parameters affecting the space, time, cost and power dimensions. Standard approaches of exploring the code compression design space are tedious, time consuming, and almost impractical with the increasing number of proposed compression algorithms. This is one of the biggest challenges faced by an architect trying to adopt a code compression methodology for a target architecture. We propose a novel synthesis based tool-chain for fast and effective exploration of the code compression design space and for evaluation of the tradeoffs. The tool-chain consists of a frontend framework that works with different compression/decompression schemes and a backend with high-level-synthesis, logic-synthesis, and power estimation tools to output the critical design parameters. We use the tool-chain to effectively analyze different code compression/decompression schemes of varying complexities.     

Effects of program compression

The size of the program code has become a critical design constraint in embedded systems, especially in handheld, battery operated devices. Large program codes require large memories, which increase the size and cost of the chip. In addition, the power consumption is increased due to higher memory I/O bandwidth. Program compression is one of the most often used methods to reduce the size of the program code. In this paper, two compression approaches, dictionary-based compression and instruction template-based compression, were evaluated on a customizable processor architecture with parallel resources. The effects on area and power consumption were measured. Dictionary-based compression reduced the area at best by 77% and power consumption by 73%. Instruction template-based compression resulted in increase in both area and power consumption and hence turned out to be impractical.     

Dictionary-based program compression on customizable processor architectures

The size of the program code has become a critical design constraint in embedded systems, especially in handheld devices. Large program codes require large memories, which increase the size and cost of the chip. In addition, the power consumption is increased due to higher memory I/O bandwidth. Program compression is one of the most often used methods to reduce the size of the program code. In this paper, dictionary-based program compression is evaluated on a customizable processor architecture with parallel resources. In addition to code density, the effectiveness of the method is evaluated in terms of area and power consumption. Furthermore, a mechanism is proposed to maintain the programmability after compression. Up to 77% reduction in area and 73% reduction in power consumption of the program memory and the associated control logic were obtained.     

面向嵌入式VLIW处理器的代码压缩技术

随着嵌入式系统的发展,在性能不断提高的同时,软件代码规模也不断扩大.而超长指令字结构更加引起了代码的膨胀,因此代码压缩技术变得很重要.本文基于自主研发的SDSP处理器核,应用3种压缩编码技术,比较它们压缩的效果,并讨论了包括压缩后地址的重映射以及解压缩结构的整体硬件方案.     

基于H.264的嵌入式视频编码器的设计与应用

设计了一种适用于工业现场的嵌入式视频编码器，视频压缩按照H.264标准，在Intel 推出的PXA255 Xscale架构的处理机和源码开放的Linux嵌入式操作系统的基础上，实现了视频的实时动态采集、压缩和网络传输，介绍了系统的研制过程，给出了系统架构和关键技术。通过构建网络测试平台，将此编码器接入以太网，服务器端将接收到的压缩码流进行实时解压、回放。此编码器可用于远程视频监控系统中前端视频的实时采集、压缩和跨IP网传输。     

COMPASS – A tool for evaluation of compression strategies for embedded processors

A major concern of embedded system architects is the design for low power. We address one aspect of the problem in this paper, namely the effect of executable code compression. There are two benefits of code compression – firstly, a reduction in the memory footprint of embedded software, and secondly, potential reduction in memory bus traffic and power consumption. Since decompression has to be performed at run time it is achieved by hardware. We describe a tool called COMPASS which can evaluate a range of strategies for any given set of benchmarks and display compression ratios. Also, given an execution trace, it can compute the effect on bus toggles, and cache misses for a range of compression strategies. The tool is interactive and allows the user to vary a set of parameters, and observe their effect on performance. We describe an implementation of the tool and demonstrate its effectiveness. To the best of our knowledge this is the first tool proposed for such a purpose.     

代码相似性检测方法与工具综述

在代码开源的潮流下,代码克隆在提高代码质量和降低开发成本的同时,一定程度地影响了软件系统的稳定性、健壮性与可维护性。代码相似性检测在计算机与信息安全发展方面具有重要的意义。为应对代码克隆带来的各种危害,目前学术界和工业界提出了很多代码相似性检测的方法,这些方法按照源代码信息处理程度可分为基于文本、词法、语法、语义和度量值5类;并开发了相应的检测工具,这些工具实现了很好的检测效果,但在大数据时代背景下也面临着数据规模不断扩大带来的一系列挑战。文中综述了代码相似性检测的方法,对5类检测方法做了详细比较;结合传统方法与机器学习技术,归类了不同检测方法对应的检测工具;按照不同评价标准评估了检测工具的检测效果,总结了每种检测方法的首选检测工具,并对未来代码相似性检测的研究方向做出了展望。     

嵌入式汽车轮胎规格号快速识别系统

针对汽车轮胎生产线检测的智能化管理问题,提出一种嵌入式系统以对轮胎规格号进行快速识别。对图像进行预处理,包括极坐标变换、双线性插值拉伸,利用大津法进行二值化,以连通域方法来提取规格号字符。采用基于统计的方法抽取轮廓特征进行规格号模式识别。系统硬件部分采用高速TMS320C6000系列DSP为核心的嵌入式硬件系统,使用参数预存储、软件流水线技术及双缓冲内存分配等优化方法。实验结果表明,该系统能快速有效地识别汽车轮胎规格号。     

Variable Length Instruction Compression on Transport Triggered Architectures

The memories used for embedded microprocessor devices consume a large portion of the system’s power. The power dissipation of the instruction memory can be reduced by using code compression methods, which may require the use of variable length instruction formats in the processor. The power-efficient design of variable length instruction fetch and decode is challenging for static multiple-issue processors, which aim for low power consumption on embedded platforms. The memory-side power savings using compression are easily lost on inefficient fetch unit design. We propose an implementation for instruction template-based compression and two instruction fetch alternatives for variable length instruction encoding on transport triggered architecture, a static multiple-issue exposed data path architecture. With applications from the CHStone benchmark suite, the compression approach reaches an average compression ratio of 44% at best. We show that the variable length fetch designs reduce the number of memory accesses and often allow the use of a smaller memory component. The proposed compression scheme reduced the energy consumption of synthesized benchmark processors by 15% and area by 33% on average.